Samsung Electronics Co., Ltd.

Tae Gyeong Chung

Sang Wook Park

Kyu Jin Lee

Do Soo Jeong

Nam Seog Kim

Il Gyu Jung

Ho Geon Song

Wan Gyan Choi

Tae Koo Lee

Won Chul Lim

A method of manufacturing semiconductor chips includes providing a semiconductor substrate including circuit regions, irradiating the semiconductor substrate with a laser beam onto to form a frangible layer, and polishing the semiconductor substrate to separate the circuit regions of the semiconductor substrate from one another into semiconductor chips. The frangible layer may be removed completely during the polishing of the semiconductor substrate.

Methods of manufacturing semiconductor chips

An apparatus for identifying a known good die according to an embodiment of the present invention includes a carrier for containing a bare semiconductor chip, a lid for covering the carrier, and a stopper for sealing the apparatus. The carrier includes: a body, in which a chip mount cavity and multiple vacuum suction holes are formed; inner connection terminals formed on a bottom surface of the chip mount cavity to communicate electrically with the bare chip; and outer connection terminals extending from the inner connection terminals to outside the body. The apparatus has an outer configuration of a conventional semiconductor package, so that the apparatus can fit into conventional test equipment. Therefore, the carrier can have a configuration of a plastic package, such as the SOP or SOJ, without a semiconductor chip. Accordingly, the apparatus according to the present invention can use conventional handling and burn-in test equipment in identifying of known good dies and thereby reduce production cost of the known good dies.

Apparatus and method for containing semiconductor chips to identify known good dies

A method for manufacturing a chip-size package and the chip-size package produced by the method uses first and second lead frames which are prepared by a stamping process. The first lead frame has leads with receiving parts, and the leads are integrally formed with lengthwise side rails of the lead frame. The second lead frame has external connections which align with the receiving parts of the leads when the second lead frame is positioned on top of the first lead frame and attached thereto. Guide holes located on the crosswise side rails of both lead frames can be used to easily align the two lead frames. A semiconductor chip is then adhered to the underside of the first lead frame, and the bonding pads of the semiconductor chip are electrically connected to the leads of the first lead frame. Then the two lead frames and the chip are encapsulated, with only the external connections of the second lead frame remaining exposed to the outside. Solder balls are then attached to the external connections for mounting onto a substrate. This chip-size package is inexpensive to produce, because the first and second lead frames can be produced by a stamping process, which is less complex and cheaper than the conventional half-etching process.

Chip-size package (CSP) using a multi-layer laminated lead frame

An inner lead bonding apparatus having a heat dissipation plate attached to inner leads and to a support for upholding a lead frame of a tape automated bonding package. The heat dissipation plate is, during performance of an inner lead bonding process, located near the bonding interface of bumps formed on a semiconductor chip or on the inner leads and the inner leads, and includes a fastener for fixing itself to the support and elliptical bolt holes for enabling its contact position to the inner leads to be controllable.

Growing community of inventors

Kyungki-do, South Korea

Tae Gyeong Chung