Moda-innochips Co., Ltd.

Innochips Technology Co., Ltd.

Tae Geun Seo

Gyeong Tae Kim

Myung Ho Lee

In Kil Park

Tae Hyung Noh

Min Soo Lee

Sang Jun Park

Ki Joung Nam

Song Yeon Lee

Heon Guk Ha

Jae Ho Han

Disclosed are a power inductor and a method of manufacturing the same. The power inductor includes a body, a coil pattern provided in the body, an external electrode disposed on at least one surface of the body and extending to at least the other surface of the body, which is adjacent thereto, and a coupling layer provided between the body and an extended area of the external electrode.

Power inductor and manufacturing method therefor

Provided is a power inductor. The power inductor includes a body including metal powder and an insulation material, at least one base provided in the body, at least one coil pattern disposed on at least one surface of the base, and an external electrode disposed on each of at least two side surfaces of the body. At least a portion of the external electrode is made of the same material as the coil pattern.

Power inductor

Provided is a power inductor. The power inductor includes a body including magnetic powder and a polymer, at least one base provided in the body and having at least one surface on which at least one coil pattern is disposed, and an insulation layer disposed between the coil pattern and the body. The body includes at least region in which the magnetic powder having a particle size different from that of the magnetic power in a remaining region is distributed.

The present disclosure discloses a circuit protection device including a first magnetic layer in which a plurality of magnetic sheets are laminated and of which at least a portion of one surface is exposed, a second magnetic layer in which a plurality of magnetic sheets are laminated and of which at least a portion of one surface is exposed, and a nonmagnetic layer in which a plurality of nonmagnetic sheets are laminated and which is disposed between the first and second magnetic layers. A noise filter part including a plurality of coil patterns is disposed in the nonmagnetic layer.

Element for protecting circuit

Provided is a laminated chip device including a first laminate in which a plurality of conductor patterns formed on a plurality of sheets are connected to each other through a via formed to penetrate at least a sheet, and a second laminate provided over or below the first laminate and having a plurality of internal electrode patterns formed on a plurality of sheets, and the internal electrode patterns have a non-conductive region in at least a portion of an area corresponding to the via.

Laminated chip device

The present disclosure relates to a stacked chip device including a first stack unit comprising a plurality of electrode patterns respectively disposed for a unit device region and common electrode patterns formed to be connected to cross the unit device regions, a second stack unit disposed on a top portion of the first stack unit and comprising a plurality of first conductor patterns, and a third stack unit disposed on a bottom portion of the first stack unit and comprising a plurality of second conductor patterns, wherein the first and second conductor patterns are formed on a plurality of sheets, the first and second conductor patterns formed on one sheet are formed across a plurality of unit device regions, and the first and second conductor patterns are connected vertically through vias formed penetrating through at least some of the sheets.

Growing community of inventors

Osan-si, South Korea

Tae Geun Seo