3com Corporation

Digital Equipment Corporation

3com Technologies

Analog Devices,inc.

Digital Equipment Corp., Patent Law Group

3com Ireland

Tadhg Creedon

Vincent Gavin

Anne G O'Connell

Denise De Paor

David J Law

Kevin Jennings

John Hickey

Suzanne M Hughes

Mike Lardner

Una Quinlan

Nicholas Mark Stapleton

Eugene G O'Neill

Kevin J Hyland

Brendan Walsh

Derek Coburn

Sean Boylan

Eugene O'Neill

Paul J Moran

John O'Dowd

Jeremy Richard Gorbold

William Paul Sherer

Terence D Lockyer

Peter J Wilson

Nigel Horspool

Susan M Pratt

Richard A Gahan

Fearghal Morgan

Katherine O'Riordan

John R Reidy

Fergus Casey

James Gibbons

Graeme J McKerrel

Eugene G O'Neil

John Morrissey

Jerome A Nolan

Deidre A Smith

Ciaran P Murphy

Con D Cremin

Richard Gahan

Padraic O'Reilly

Jeremy Gorbold

John Reidy

An exemplary method and system of addressing an integrated circuit within a daisy chain network. In the exemplary method, the address of the integrated circuit may be initialized to a predetermined initial address. The integrated circuit may receive a command that includes a type identifier and an address field. Based on the type identifier, the type of command may be determined. As a result of the determination, reading the address from the address field. The read address may be stored in a register. The address may be modified, and may be output. Upon receipt of the data or a command, the integrity of the data including data within the received command, may be confirmed by an error checking algorithm.

Addressable integrated circuit and method thereof

Automatic range shifting for an analog to digital converter (ADC) includes combining an external analog input and a DAC output to provide an input to the ADC, detecting whether the range of the output of the ADC is above a predetermined upper range limit or below a predetermined lower range limit, and generating an adjustment code to increase the DAC output if the ADC output is above the upper range limit and to decrease the DAC output if the ADC output is below the lower range limit for decreasing the ADC input when the ADC output is above the upper limit and to increase the ADC input when the ADC output is below the lower limit to keep the ADC input within the ADC range.

Automatic range shift system and method for an analog to digital converter

A system transfers a data stream including data packets separated by non-packet words from a first clock domain to a second clock domain. It includes an elasticity buffer into which the data stream is written in a cyclic sequence under the control of the clock frequency in the first clock domain and from which the data stream is read out in a cyclic sequence under the control of the clock frequency in the second domain. The two sequences are monitored to provide an anticipatory signal indicating that the reading sequence approaches proximity to the writing sequence. A non-packet word is inserted into the data stream in the first domain. In the second clock domain the existence of the inserted non-packet word is detected and the buffer is caused to advance the reading cycle thereby to discard the said inserted non-packet word.

System for detection of asynchronous packet rates and maintenance of maximum theoretical packet rate

A program tool automatically generating interconnect logic for a system-on-a-chip is based on a library of operational cores and on a architecture which requires all data exchange between cores to proceed via shared memory, which may be 'off-chip'. The architecture includes a data aggregation technique for access to memory with successive levels of arbitration.

Automatic generation of interconnect logic components

An architecture for a system on a chip wherein functional cores have wrappers for compatibility with a common bus system and the bus system includes aggregators for bus transactions of different speeds and/or bus widths.

Asic system architecture including data aggregation technique

A stackable network unit which can form a ring with other units has a master mode in which it can place packets on the ring, so that they can be ultimately forwarded from other units, and a repeat mode in which it can make a request for transfer of mastership of the ring, inserting bits in a header of an arbitration packet. If a master unit has completed the transmission of a packet and, preferably, after the required inter-packet gap has elapsed, it has not yet received an arbitration header to permit the making of an arbitration decision it can transmit a subsequent packet. The header information of this packet indicates to the other units that this subsequent packet is part of a burst of packets and the other units should not set requests in the header of this packet because this packet would not be used for arbitration. The master unit indicates the nature of the subsequent packet by setting a sequence number in the header of the packet to distinguish it and following packets in a burst from the 'first' packet which is the one used to pick up requests from the units that may need to become the master unit.

Stackable ring network including burst transmission of data packet

DRAM refresh command operation

A clock scheme for a system on a chip wherein integral sub-multiples of a system clock have positive edges on odd-numbered positive edges of the system clock and negative edges on even-numbered positive edges Data transfer between blocks of different frequencies is controlled by a state machine of the higher frequency block and can be achieved without elastic buffers and/or synchronizers.

Clocking scheme for ASIC

An application specific integrated circuit includes a multiplicity of operative circuit blocks. Disposed in at least one of the blocks is a multiplicity of selectively operative heater modules for providing localised heating within the block. The heater modules may comprise cyclic redundancy code generators each coupled to respond to a system clock, and each heater module may include a system clock divider providing a multiplicity of differently divided clock signals and means for selecting a clock signal for use by the module. The invention is useful in design variable testing to produce variation with temperature of the frequency of an intermittent timing error.

Method and apparatus for inducing locally elevated temperatures in an application specific integrated circuit

A method of operating a repeater for a packet-based data transmission system wherein the repeater has a receiving port associated with a buffer whereby packets received at the port are temporarily stored before they are onwardly transmitted and wherein the repeater performs a contention resolution process such that if an attempted onward transmission of a packet is prevented by virtue of contention with a prior or an existing transmission, a subsequent attempt at transmission of that packet is delayed for a time which is likely to be substantially greater than a selected minimum time. The method includes examining a received packet to determine whether the packet is a multi-media packet, and giving the packet a higher priority in the contention resolution process such that if the packet is not transmitted onwardly owing to contention with a prior transmission, a fresh attempt at transmission of the packet is made on the expiry of the selected minimum time.

Method for transmitting multimedia packet data using a contention-resolution process

An interface comprises a management entity including a first state machine, a bidirectional serial data bus and a clock line, intended for connection to physical layer devices each of which includes at least one register into which data can be written by way of the serial data bus and at least one register from which data can be read by way of the serial data bus, the management entity providing a clock signal having transitions defining bit periods for said data and further comprising a line driver for the serial data bus and an amplifier which is connected to sense the voltage level of the data bus. The management entity is organised to detect during a specified period while the line driver is quiescent whether the physical layer device is present or not according as the voltage of the bus approaches that of a voltage supply rail in the physical layer device or that of a datum for the management entity. The management entity is arranged to cause the line driver to drive the bus towards the voltage of the supply rail in an interval between the penultimate clock transition before the beginning of said time period and the clock transition denoting the beginning of said time period. The said interval may occur during a reading cycle of the management entity and, in accordance with IEEE Standard 802.3 Clause 22, the reading cycle may be defined to include an address word identifying a register in a physical layer device and a turn around time before the physical layer device provides data and wherein said interval occurs after the provision of a final bit in said address word when the final bit is such as to drive the bus toward the datum.

Method and apparatus for the detection of the presence of a device on a high speed digital data bus

A system is provided that protects a network from storms of multicast/broadcast data. The system includes a switch or bridge which monitors traffic through it in order to detect the onset of a storm condition from previous receptions of requests for multicasts or broadcasts. Each port or bridge or switch has associated with it one data bit which can be controlled to prevent a storm of multicasts/broadcast data being forwarded to all parts of the switch and jamming the system.

Storm protection mechanism

A repeater for a computer network, and a network incorporating such a repeater are described in which repeater communication addressed to a subset of the devices connected to the repeater are transmitted in a corrupt or scrambled form to other network devices. The processing load is thus reduced for such other network devices, in particular in the context of high volume multicast traffic such as in video conferencing.

Multicast filtering

Apparatus for controlling data flow using lookup tables to link incoming

A network device for use in a data communication network comprises: a multiplicity of ports capable of receiving input data; a common buffer memory for storing in respective buffers data received by the input ports; and processing system for controlling the writing of data into buffers and the reading of data from said buffers. The processing system determines whether the extent of occupation of the common buffer memory exceeds a threshold defined to represent congestion of the memory. Counter system enabled by the processing system on detection of the aforementioned threshold count units of input data through the respective ports, the processing system decrementing these counters as data is read out from the common buffer memory.

Multi-port communication network device including common buffer memory

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Furbo, Ireland

Tadhg Creedon