Integrated Device Technology, Inc.

Pmc-sierra, Inc.

Tadeusz Kwasniewski

Tingjun Wen

David Walter Carr

Kris Iniewski

Fangxing Wei

Lizhong Sun

An integrated circuit comparator is provided that determines non-strict inequalities between operands applied thereto. Each comparator includes at least one n-bit comparator cell. This comparator cell is configured to determine a non-strict inequality between a first n-bit operand (e.g., A[n&#x2212;1, . . . , 0]) and a second n-bit operand (e.g., B[n&#x2212;1, . . . , 0]). The comparator cell determines the non-strict inequality by computing a control output signal C(or its complement), where: 'n' is a positive integer greater than one and Cis a control input signal that specifies an interpretation to be given to the control output signal C.

Packet processors having comparators therein that determine non-strict inequalities between applied operands

A multi-functional match cell is responsive to first and second n-bit operands and configured so that the match cell operates as an n-bit range match cell when the first and second n-bit operands are equivalent, as an n-bit NOR-type CAM cell when the second n-bit operand is masked and as an n-bit NAND-type CAM cell when the first n-bit operand is masked, where 'n' is a positive integer greater than one.

Packet processors having multi-functional range match cells therein

A method of phase detecting a data input NRZ signal comprises applying the input data signal to a pair of parallel channels each comprising the same phase delay, and each clocked using the same clock signal. The phase delayed input data signal is coupled to respective inputs of a pair of phase comparators. The input data signal is coupled to a further channel comprising the same phase delay, and the further channel is clocked using the same clock signal. The phase delayed input signal is passed from the further channel through a further delay which is a fraction of that same phase delay, and the further delay is clocked using the clock signal. The further delayed input data signal is applied to another input of one of the phase comparators. The input data signal is applied through another phase delay which has the fraction of the aforenoted same phase delay (but is unclocked), to another input of the other of the phase comparators. Output signals are obtained from each of the phase comparators.

Pipelined phase detector for clock recovery

A ring oscillator comprising: a plurality of sub-feedback loops, each comprising a pair of serially connected inverters and a feedback inverter having its input coupled to the output of the pair of inverters and its output connected to the input of the pair of inverters, the pairs of inverters being connected in a ring, and a downstream inverter of each respective pair of inverters forming an upstream inverter of an immediately following pair of inverters.

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Ottawa, Canada

Tadeusz Kwasniewski