Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Tadayuki Shimizu

Masaki Tsukude

Shigeki Ohbayashi

Hirotoshi Sato

Minoru Senda

Takafumi Takatsuka

Shinichi Kobayashi

Kunihiko Kozaru

A semiconductor integrated circuit which is supplied with a first power supply voltage and a second power supply voltage from outside so as to operate incorporated circuits, and outputs data at an output terminal, includes an internal circuit that carries out a predetermined function for an input signal, an output circuit which includes a first circuit for converting the signal from the internal circuit into an output signal and a second circuit containing a final stage buffer circuit which outputs, depending on the signal from the first circuit, data to the output terminal; and a switching circuit that switches a power supply voltage supplied to the second circuit, to either the first power supply voltage or the second power supply voltage. A voltage obtained by decreasing the first power supply voltage is supplied to the internal circuit. The first power supply voltage is supplied to the first circuit.

Output buffer circuit with power supply voltages different from a power supply voltage applied to an internal circuit

The semiconductor integrated circuit incudes an input circuit which receives a signal, an internal circuit which applies a predetermined function to the received signal, and an output circuit which outputs the signal applied with the predetermined function. An external power supply voltage VDD and an IO power supply voltage VDDQ which is lower than the voltage VDD are supplied to the semiconductor integrated circuit. A voltage VIO obtained by decreasing the external power supply voltage VDD is supplied to the input circuit. The IO power supply voltage VDDQ is supplied to the output circuit.

Semiconductor integrated circuit

In a power on reset (POR) circuit, when power is turned on, an output signal of an inverter attains an H level and an N channel MOS transistor is rendered conductive. The potential of an input node of the inverter becomes a potential of a power supply voltage divided by a conductive resistance value R1 of a P channel MOS transistor and a conductive resistance value R2 of an N channel MOS transistor. Assuming that the threshold voltage of the inverter is 0.8 V and R1:R2&equals;2:3, then the power supply voltage Vres at the time when signal POR&num; inverts its level becomes 1.33 V. Thus, this POR circuit can reliably be utilized even in a product designed to operate with 1.5 V incorporating a MOS transistor having a threshold voltage of 0.8 V.

Power on reset circuit

The semiconductor memory device of the invention has a refresh timer for generating a refresh clock, a refresh executing circuit for sequentially refreshing a plurality of memory cells part by part on the basis of the cycle of the refresh clock, and a refreshing control circuit disposed between the refresh timer and the refresh executing circuit, for stopping transmission of the refresh clock from the refresh timer to the refresh executing circuit in a predetermined period during which the cycle of the refresh clock is easy to become unstable. With the configuration, an erroneous operation of the refresh executing circuit can be prevented.

Semiconductor memory device having refreshing function

A dynamic-type memory A, a non-volatile memory B and a static-type memory C are enclosed in one package. Separated from a first terminal supplying a power-supply potential to the memories A and B, a second terminal supplying a power-supply potential to the memory C is provided. By stopping the supply of the power-supply potential to the first terminal at stand-by, stand-by current of a semiconductor memory device can be reduced. Therefore, the semiconductor memory device having an increased memory capacity while reducing a mounting area and consumption current at stand-by can be provided.

Semiconductor memory device having increased memory capacity while reducing mounting area and stand-by current

An output buffer includes first current driving units connected in parallel between a power-supply voltage and an output node; second current driving units connected in parallel between a ground voltage and an output node; a plurality of operation selection circuits setting the respective first and second current driving units to be in either activated or inactivated state in a non-volatile manner; first signal transmission circuits arranged respectively corresponding to the first current driving circuits and each transmitting the level of output data with a similar first propagation time period; and second signal transmission circuits arranged respectively corresponding to the second current driving units and each transmitting the level of the output data with a similar second propagation time period.

Output buffer capable of adjusting current drivability and semiconductor integrated circuit device having the same

In a power on reset (POR) circuit, when power is turned on, an output signal of an inverter attains an H level and an N channel MOS transistor is rendered conductive. The potential of an input node of the inverter becomes a potential of a power supply voltage divided by a conductive resistance value R of a P channel MOS transistor and a conductive resistance value R of an N channel MOS transistor. Assuming that the threshold voltage of the inverter is 0.8 V and R :R , then the power supply voltage Vres at the time when signal POR&num; inverts its level becomes 1.33 V. Thus, this POR circuit can reliably be utilized even in a product designed to operate with 1.5 V incorporating a MOS transistor having a threshold voltage of 0.8 V.

In a test mode, a first switch circuit is inactivated, and second and third switch circuits are activated. The oscillation frequency of a ring oscillator can be measured by measuring a delay value from the time a signal is input from a node inputting a test signal to the time it is output through the second switch circuit, inversion and delay circuit and the third switch circuit. Therefore, a semiconductor device capable of a simple measurement of the oscillation frequency can be provided.

Semiconductor device capable of simple measurement of oscillation frequency

In a power on reset (POR) circuit, when power is turned on, an output signal of an inverter attains an H level and an N channel MOS transistor is rendered conductive. The potential of an input node of the inverter becomes a potential of a power supply voltage divided by a conductive resistance value R of a P channel MOS transistor and a conductive resistance value R of an N channel MOS transistor. Assuming that the threshold voltage of the inverter is 0.8 V and R :R &equals;2:3, then the power supply voltage Vres at the time when signal POR&num; inverts its level becomes 1.33 V. Thus, this POR circuit can reliably be utilized even in a product designed to operate with 1.5 V incorporating a MOS transistor having a threshold voltage of 0.8 V.

An IC socket that can improve the efficiency of the lead replacement process and a semiconductor device having such an IC socket are provided. The IC socket is removably mounted on a circuit substrate, and includes a plurality of linear lead members, a lead module, and a socket base body. The lead module is replaceable and holds lead members of each group of a plurality of groups into which the plurality of lead members are divided. The lead module is provided in plurality to hold each of the plurality of groups. The socket base body is placed between the circuit substrate and the lead module and determines the position of the lead module on the circuit substrate.

IC socket and semiconductor device with replaceable lead members

A semiconductor device comprising: a power source voltage detecting member for outputting a voltage detection signal in accordance with a power source voltage; and a delay member which includes an input portion for receiving an input signal, a plurality of delay portions connected to the input portion, a selective portion for selecting one of the delay portions in accordance with the voltage detection signal and an output portion for outputting a delay signal obtained by delaying the input signal by the one of the delay portions.

Semiconductor device having a delay circuit for adjusting the timing of control signals

A semiconductor device includes a sense amplifier which becomes able to amplify a signal when receiving a read enable signal; a delay unit which can provide a plurality of transmission paths having different delay times and which propagates the read enable signal through a transmission path corresponding to a selection signal among the plurality of transmission paths; a selection signal generation circuit capable of generating the plurality of selection signals; and a JTAG boundary scan test circuit which brings the selection signal generation circuit into operation in accordance with a instruction.

Selectable sense amplifier delay circuit and method

Multi-function pins are provided for executing input of address bits and input/output of data bits. Address input enable signal and data I/O enable signal supplied from independent pins determine one between the address input and the data input/output to be performed by the multi-function pin. One of an address register, a data input register and a data output register provided for each multi-function pin operate in response to a combination of signal levels of the address input enable signal and the data I/O enable signal.

Growing community of inventors

Hyogo, Japan

Tadayuki Shimizu