Hitachi, Ltd.

Tadayuki Sakakibara

Teruo Tanaka

Yoshiko Tamaki

Yasuhiro Inagami

Katsuyoshi Kitai

Tadaaki Isobe

Yuji Tsushima

Hideya Akashi

Masanao Ito

Shigeko Hashimoto

Satoshi Muraoka

Isao Ohara

Shigeko Yazawa

Hiromitsu Maeda

Masaru Koyanagi

Disuke Yamane

In an information processing system including one or a plurality of processors, a diagnostic program is executed with a predetermined frequency to diagnose the processors. The diagnostic program generates one or a plurality of processes or threads at a predetermined frequency, at predetermined time intervals, for example, to diagnose the processors. A generated process or thread executes diagnosis on each processor, and the process or thread that detected a fault in the processor finishes its execution by storing fault information in storage. The process or thread of another processor other than the faulty processor refers to the fault information about the faulty processor and executes a troubleshooting process.

Method for processing a diagnosis of a processor, information processing system and a diagnostic processing program

A cache data control system and method for a computer system in which in a memory read processing, a coherent controller issues an advanced speculative read request for (speculatively) reading data from a cache data section in advance to a cache data controller, before reading a cache tag from a cache tag section and conducting cache hit check. If a cache hit has occurred, the cache data controller returns the data subjected to speculative reading as response data, at the time when the cache data controller has received a read request issued by the coherent controller.

Computer system utilizing speculative read requests to cache memory

A cache controller stores pre-set variables for pre-fetch block size and stride value. A cache controller receives an access request for the main memory from the processor, and generates a pre-fetch request based an the access request and the variables. The cache controller reads data from main memory based on the generated pre-fetch request and writes this data to the cache memory.

Cache control method and cache controller

Computer system

In a multiprocessor computer system, individual vector processors are provided with priority switching signal control circuits, respectively, and a storage control unit incorporating a priority control circuit. Priority bit information is provided for priority circuits incorporated in the storage control unit. Paths for priority switching signal issued in accordance with a number of requests as generated and types of instruction generating the requests are provided between the priority switching signal control circuits and the priority control circuit of the storage control unit, while paths for the priority switching signal as generated are provided between the priority control circuit and all the priority circuits.

Priority control with concurrent switching of priorities of vector

In order to make use of row address lock mode of operation of a plurality of memory banks comprising synchronous DRAMs or the like and divided into a plurality of real bank groups, for example, for example, more than the memory banks are grouped into a plurality of logical groups each spanning the real bank groups. Addresses are allocated in unit of each logical group in a block-interleaving manner. When a series of requests issued by a given requester include a plurality of requests for accessing the same row address in the same memory bank, that requester requests that the row address be locked for access by the plurality of requests. The lock request is retained by a row address management unit. When a succeeding request from another requester requests access to a row address other than the locked address in the same memory bank, a priority circuit selects a predetermined number of requests from the initial requester having locked the memory in preference to a request made by the other requester.

Processor system having address allocation and address lock capability

Interprocessor priority control system for multivector processor

A vector processor includes a storage control apparatus which incorporates an access request buffer unit equipped with an address decoding unit having address decoder circuits corresponding to all models of the vector processors belonging to a same machine series. By using model ID signals, the address decoding is selectively enabled by a selector. The address decoding unit equalizes the periodicities at which the address assignments to the memory modules are skewed or shifted for all the element parallelism factors of the processors belonging to the same machine series. Access request queue is provided in a necessary number of stages in precedence to an access request priority determining unit incorporated in the storage control apparatus.

Vector processor adopting a memory skewing scheme for preventing

A vector processor system for processing vector instructions and scaler instructions fetched from storages includes a memory storage, a first and a second scaler processing units connected to the memory storage, a vector processing unit being connected to the memory storage and the two scaler processing units and for processing a vector instruction fetched from the memory storage during processing of scaler instruction/vector instruction separate type programs and a vector instruction received from the second scaler processing unit during processing of scaler instruction/vector instruction mingled type programs. More particularly, for scaler instruction/vector instruction mingled type programs, the vector processing unit receives the vector instruction from the scaler processing unit, whereas for scaler instruction/vector instruction separate type programs, the vector processing unit retrieves the vector instruction directly from the memory storage.

Vector processing apparatus for processing different instruction set

In a multiprocessor system having a plurality of main memories and a shared extended memory, each main memory is associated with an extended memory partial write control. When an extended memory partial write instruction is issued, tag information identifying updated portions of main memory data is transferred to the associated extended memory partial write control along with the main memory data. Each time a subblock of the main memory data arrives, the extended memory partial write control performs a partial write operation to substitute those portions of the main memory data which are identified by the tag information for the corresponding portions of a data subblock in a specified extended memory area. During this partial write operation, that specified extended memory area is kept locked.

Method and apparatus for parallel processing of a large data array

A plurality of storage control units are employed in the storage control unit section; moreover, two requester modules are adopted in association with these storage control units. Each memory module is constituted with as many access bank groups as there are storage control units. The access bank groups operate in concurrent fashion and are accessible from any one of the storage control units. In the element assignment, a plurality of request control units in each requester module and a plurality of vector data controllers in each vector register unit are respectively assigned with serial numbers beginning from zero. For a vector data controller, a number assigned thereto is divided by the request module count to attain a remainder such that the vector data controller is assigned to a request module having a number identical to the value of the remainder. Furthermore, a request queue is disposed at a stage preceding each priority unit and a request send-out unit is arranged to store therein a state of the request queue and to control a request transmission from each request control unit. Addresses are assigned to the respective memory modules, bank groups, and banks according to skew schemes respectively suitable therefor.

Vector processor with a memory assigned with skewed addresses adapted

A parallel processing system includes tightly coupled multiprocessors. Each multiprocessor incorporates a local extended storage device which is a secondary storage device for a main storage device. The tightly coupled multiprocessors are connected with each other through a shared extended storage device. A compiler or preprocessor for the system analyzes the data to be allocated on the extended storage devices so that large scaled data accessed from each tightly-coupled multiprocessor are allocated on the local extended storage whereas the data to be accessed from a plurality of tightly-coupled multiprocessors are allocated on the shared extended storage.

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Kunitachi, Japan

Tadayuki Sakakibara