Kioxia Corporation

Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kaisha Toshiba

Tadayoshi Uechi

Takashi Izumida

Takeshi Shimane

Masaki Kondo

Takashi Ichikawa

Daiki Kiribuchi

Soh Koike

Satoru Yokota

Tetsuya Yamashita

Takuyo Nakayama

Nobutoshi Aoki

Tsukasa Nakai

Takeichiro Nishikawa

Takahisa Kanemura

Hiroki Tokuhira

Hikari Tajima

Takashi Kurusu

Michihito Kono

An information processing apparatus has an output data acquisition unit configured to acquire an output value obtained by performing an experiment or simulation based on an input parameter of a predetermined number of dimensions, an evaluation value calculation unit configured to calculate and output an evaluation value of the output value, an outlier processing unit configured to output a converted evaluation value including a specified value obtained by converting the evaluation value that does not satisfy a predetermined criterion, a next input parameter determination unit configured to determine a next input parameter based on the input parameter and the converted evaluation value corresponding to the input parameter, and an iteration determination unit configured to repeat processing of the output data acquisition unit, the evaluation value calculation unit, the outlier processing unit, and the next input parameter determination unit until a predetermined condition is satisfied.

Information processing apparatus and information processing method

A semiconductor device has a third region between first and second regions on a substrate surface. A gate insulating film which is above the third region. A gate electrode is above the gate insulating film and includes a metal-containing layer. A first conductor is above the gate electrode. A first voltage can be applied to the first conductor. A second conductor is above the first region. A second voltage can be applied to the second conductor. A third conductor is above the first region. A third voltage different from the first and second can be applied to the third conductor. A metal oxide film is provided between the first region and the third conductor. An upper surface of the metal oxide film includes a portion at a height from the substrate that is lower than a height of an upper surface of the metal-containing layer.

Semiconductor device and semiconductor storage device

An information processing apparatus according to an embodiment of the present invention includes an estimator and a recommender. The estimator is configured to, based on a data set including a set value set for a parameter and an evaluation value or an evaluation value variation where the set value is set for the parameter, estimate a relationship between the set value and the evaluation value variation. The evaluation value variation indicates a variation of respective evaluation values where a plurality of values included within a neighborhood range that is based on the set value are set for the parameter. The recommender is configured to, based on the estimated relationship, determine a recommended set value.

Information processing apparatus, information processing method, and non-transitory computer readable medium

A semiconductor memory device, includes: a first region including a memory cell array; and a second region including a peripheral circuit. The second region includes a semiconductor substrate having a first surface and a second surface. The semiconductor substrate includes: a semiconductor region between the first and second surfaces; an n-type semiconductor region provided on the first surface and higher in donor concentration than the semiconductor region; a damaged region provided on the second surface; and a p-type semiconductor region provided between the damaged region and the n-type semiconductor region, closer to the second surface than the n-type semiconductor region in a direction from the first surface toward the second surfaces of the semiconductor substrate, and higher in acceptor concentration than the semiconductor region.

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a first stacked body in which a plurality of first conductive layers are stacked at intervals in a first direction above a semiconductor substrate; a second stacked body in which a plurality of second conductive layers are stacked at intervals in the first direction above the semiconductor substrate; and a first slit extending in a second direction perpendicular to the first direction, the first slit isolating the first stacked body and the second stacked body in a third direction perpendicular to the first and second directions.

A semiconductor device of an embodiment includes: a first and second semiconductor regions of a first conductivity type; a third semiconductor region of a second conductivity type disposed between the first and second semiconductor regions; a fourth semiconductor region of the first conductivity type disposed below the first semiconductor region; a fifth semiconductor region of the first conductivity type disposed below the second semiconductor region; a first region containing carbon disposed between the first and fourth semiconductor regions; a second region containing carbon disposed between the second and fifth semiconductor regions; a third region disposed between the first and second regions; the first and second regions having a first and second carbon concentrations respectively, the third region not containing carbon or having a lower carbon concentration than the first and second carbon concentrations in a portion below an end of a lower face of a gate electrode.

Semiconductor device

According to one embodiment, a semiconductor device includes an element region, an element isolation region adjacent to the element region, a gate insulating layer provided on an upper surface of the element region, and a gate electrode including a semiconductor layer, the semiconductor layer containing boron (B) and including a portion provided on the gate insulating layer, the element isolation region including an upper portion including an upper surface of the element isolation region and a lower portion including a lower surface of the element isolation region, and the upper portion of the element isolation region applying compressive stress to a portion of the element region, which is adjacent to the upper portion of the element isolation region.

A semiconductor device according to an embodiment includes a semiconductor layer having a first plane and a second plane opposite to the first plane; a gate electrode; a gate insulating layer provided between the first plane and the gate electrode; and a pair of first p-type impurity regions provided in the semiconductor layer on both sides of the gate electrode, containing boron, carbon, and germanium, having a bond structure of boron and carbon, having a first boron concentration and a first depth in a direction from the first plane toward the second plane, and having a distance between the first p-type impurity regions being a first distance.

Semiconductor device and semiconductor memory device

A non-volatile memory device includes a conductive layer, a first electrode layer provided side by side with the conductive layer in a first direction, a second electrode layer provided between the conductive layer and the first electrode. At least a part of the second electrode on the conductive layer side has a work function smaller than a work function of the first electrode. The device further includes a first channel body extending through the first electrode layer in the first direction and a charge storage portion provided between the first electrode layer and the first channel body.

Non-volatile memory device

An integrated circuit device according to an embodiment includes a semiconductor substrate, a first semiconductor member and a second semiconductor member provided on the semiconductor substrate, a first electrode disposed between the first semiconductor member and the second semiconductor member, and a second electrode disposed between the semiconductor substrate and the first electrode. The first semiconductor member and the second semiconductor member extend in a first direction perpendicular to an upper surface of the semiconductor substrate. The first semiconductor member and the second semiconductor member are separated in a second direction orthogonal to the first direction. The first electrode extends in a third direction intersecting both the first direction and the second direction. The second electrode extends in the third direction.

Growing community of inventors

Kawasaki Kanagawa, Japan

Tadayoshi Uechi