Fujitsu Corporation

Other

Tadayoshi Katoh

Hiroshi Kurihara

Atsushi Yamashita

Takashi Saito

Kaneyasu Shimoda

Hiroshi Okubo

Hideaki Yokoyama

Kazuhisa Matsushima

Takashi Ishida

Shuichi Murakami

Hiroshi Yazawa

Tadashi Nakamura

Toshio Ohta

Eiji Itaya

Takao Sasaki

Sadao Takenaka

Yuzo Ageno

Masaru Moriwake

A digital audio reproducing apparatus including a receiver receiving modulated data, a demodulator demodulating the modulated data received by the receiver, an audio decoder decoding, in a unit of a frame, digital audio information contained in the modulated data demodulated by the demodulator, and an audibility corrector for effecting audibility correction on failing digital audio information contained in a frame that failed to be decoded, when the audio decoder fails to decode the digital audio information.

Digital audio reproducing apparatus

A laminated structural body is manufactured by laminating unidirectionally arranged strands and a web such that two layers of the web sandwich the strands therebetween. A cylindrical web is delivered in a direction parallel to a central axis thereof. A polymer liquid is discharged from a spinning head, which is disposed in the cylindrical web and rotated about the central axis of the cylindrical web, toward an inner surface of the cylindrical web to spin strands of the discharged polymer liquid. The spun strands are arranged in a direction substantially parallel to the circumferential direction of the cylindrical web and laminated on the inner surface of the cylindrical web. The cylindrical web with the strands laminated thereon is folded flatwise to sandwich the strands between the two folded layers of the web.

Laminated structural body having unidirectionally arranged strands sandwiched between two web layers, and method of and apparatus for efficiently manufacturing such laminated structural body

The present system comprises a transmitting apparatus for digital broadcast which includes an original signal generating section, delaying section, information amount reducing section, and transmitting section. A receiving and reproducing apparatus for digital broadcast includes a signal reception front stage unit for receiving a high quality signal and a low quality signal, mode determining section and reproducing section composed of a delaying section and selecting section for selectively reproducing the high quality signal and the low quality signal. By employing time diversity, the transmitting apparatus sends the low quality signal having a smaller bandwidth and the high quality signal so that the low quality signal has a preceding time lag relative to the high quality signal, and the receiving apparatus reproduces broadcasting programs. Utilizing the frequency band for broadcast effectively, many broadcasting programs can be increased, and the investment for providing a gap filler can be minimized.

Method, system and apparatus for transmitting, receiving, and reproducing a digital broadcast signal

The system allows a plurality of earth stations to communicate with one another by relaying transmission signals via satellites circling the earth in high earth and low earth orbits. A geostationary satellite operates in a geostationary orbit, while a plurality of low-earth orbiting satellites circle the earth in low-earth orbits. Those satellites serve as repeaters for the communications between a first earth station and a second earth station. Tracking relay means, disposed in the geostationary satellite, tracks only a limited number of low-earth orbiting satellites within an orbital range that corresponds to a predetermined area on the earth. Accordingly, the tracking relay means relays transmission signals of the second earth station to the low-earth orbiting satellites only when they are within the orbital range.

Dual layer satellite communications system and geostationary satellite

A path trace Viterbi decoder comprising an ACS circuit for generating a path selecting signal, a path memory for storing the path selecting signal, a node calculator for calculating the node number of a most likely path on the basis of the data read out from the path memory, and a trace memory for storing the most likely path data, etc. The node number data of the most likely path calculated by the node calculator is stored in the trace memory and the decoding operation is carried out by using the data read from the trace memory.

Path trace viterbi decoder

An integrated viterbi decoder structure and method, the viterbi decoder receives test input signals at a distributor, an ACS circuit and a path memory and compares the output signals generated by the test input signals with predetermined test signals so as to test the internal operations of the viterbi decoder without the need for complex logic housed with the viterbi decoder.

Viterbi decoder and method for testing the viterbi decoder

A sequential decoding device for decoding a data expressed by a systematic code having a symbol memory, a maximum likelihood path decision circuit, and a path memory, includes: an overflow detection circuit for detecting an overflow of the symbol memory, and a switch for supplying signal bit data, as an decoded output, read from the symbol memory directly to the path memory in correspondence with an overflow detection signal from the overflow detection circuit. The device includes further a path metric value increase/decrease monitoring circuit for monitoring the increase/decrease of a path metric value delivered from the maximum likelihood path decision circuit and controlling the switch in such a manner that, when a monotonous increase of path metric value is detected, the decoded output of the maximum likelihood path decision circuit is supplied to the path memory instead of a direct supply of the decoded output of the symbol memory to the path memory.

Sequential decoding device for decoding systematic code

A Viterbi decoder with a pipeline processing function for decoding a received code sequence transferred from an encoder, including correlation determining circuit for calculating correlation between a received code sequence and each of a plurality of predetermined code sequences of known allowable transitions; and selecting circuits operatively receiving the correlations for selecting one of the predetermined code sequences as the maximum likelihood transition. The selected one of the predetermined code sequences has the maximum correlation among the correlations. A decoded code sequence is obtained from the selected one of the predetermined code sequences. The correlation determining circuit includes a plurality of new correlation determining circuits each for determining a new correlation based on newly received code sequence and an aready calculated correlation between the already received code sequence and one of the predetermined code sequences; and a comparing circuit for comparing, simultaneously with the determination of the new correlations, already calculated correlations between the already received code sequence and the predetermined code sequences, so as to output a path selecting data. The selecting circuits selects, in response to the selecting data, one of the predetermined code sequences as the maximum likekihood sequence with respect to the code sequence generated by the encoder.

Viterbi decoder with the pipeline processing function

A band-pass filter circuit comprising a band-pass filter for removing noise modulation components from an input signal comprising a carrier sine wave, a phase detector for detecting a phase difference between input and output signals of the band-pass filter, a loop filter supplied with the output from the phase detector, and automatic control means for effecting control by the output from the loop filter so that a difference between the frequency of the input sine wave and the center frequency of the band-pass filter is reduced to zero. For carrier recovery in a burst mode, the loop filter is selected for each particular case so that high-speed pulling-in is possible even if a narrow-band filter is employed as the band-pass filter for the removal of noise components. Also, high-speed and high-precision pulling-in is achieved when many bursts of different frequencies are applied in one frame period. Further, when common and individual frequency variations occur at the same time, high-speed pulling-in is also achieved for each burst.

Band-pass filter circuit

A method and circuit for generating a pseudo-error signal comprising a demodulator circuit for demodulating an input signal; a first discriminator circuit for regenerating a first digital data signal by discriminating the output of the demodulator circuit; a noise extracting means for extracting a noise component from the input signal; an adding circuit for adding the output of the noise extracting means and the output of the demodulator circuit; a second discriminator circuit for regenerating a second digital data signal by discriminating the output of the adding circuit, and; an exclusive OR circuit for recognizing whether or not the first digital data signal coincides with the second digital data signal.

Method for generating a pseudo-signal in an error rate supervisory unit

A carrier regeneration circuit regenerates the carrier from the QAM (Quadrature Amplitude Modulated) received signal, as produced and transmitted by a quadrature partial response modulation system wherein quadrature-related carriers (i.e., having a phase difference of 90.degree.) of the same frequency are amplitude modulated with two parallel signals which have been subject to partial response conversion. The carrier regeneration circuit comprises a probability decision circuit which decides the probability of generation of particular demodulated data code combinations, and a carrier regeneration control circuit which maintains the phase ambiguity of the regenerated carrier within an integer multiple of 90.degree.. The control circuit responds to the output of the probability decision circuit for selectively shifting the phase of the regenerated carrier by 45.degree..

Carrier regeneration circuit

A communication system combines partial response and quadrature amplitude modulation systems. Two parallel input signals supplied for transmission are processed by a differential logic circuit which produces two parallel output signals, in turn supplied to respective pre-coding circuits and subsequently to corresponding partial response converter circuits. Corresponding modulators receive the thus processed two parallel signals for amplitude modulation of respective quadrature-related carrier signals and for combining same for QAM transmission. The differential logic circuit examines the parallel input signals and, for a code combination thereof wherein the code combination would not be influenced by the 90.degree. phase ambiguity of the regenerated carrier during demodulation in the receiver, the parallel input signals received thereby are applied directly to the pre-coding circuits; conversely, where the code combination of the parallel input signal code combination would be influenced by the 90.degree. phase ambiguity of the regenerated carrier during the aforesaid demodulation, the two parallel input signals are processed in accordance with the differential logic processing prior to supply to the pre-coding circuit. Particularly, when the input signals P.sub.n, Q.sub.n are (1,1) or (0,0), they are applied directly to the pre-coding circuit; when (0,1) the preceding transmitting vector position is maintained, and when (1,0), the differential logic changes the phase thereof by .+-.90.degree. from the preceding transmitting vector position. The preceding transmitting vector is defined as that vector corresponding to the next preceding signal code combination (1,0) or (0,1), skipping any vector corresponding to a code combination (0,0) or (1,1) which may intervene. In the receiver, a corresponding differential logic circuit is provided, whereby the output data in the receiver is accurately reproduced in accordance with the originally transmitted data, independently of the phase ambiguity of the phase of the regenerated carrier in the receiver.

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Kawasaki, Japan

Tadayoshi Katoh