Nec Corporation

Tadayoshi Enomoto

Masakazu Yamashina

Masaaki Yasumoto

Masato Motomura

Hiroshi Hayama

Hachiro Yamada

A motion picture coder for coding plural macro blocks of motion picture data based on a standardizing system is disclosed. The coder comprises first and second pipe-lined processors executing different coding processes respectively, both of which are separated from one another so as to accomplish a parallel operation thereof. The first processor executes a motion vector detection for a second macro block, an inter-frame addition for a first macro block and an inter-frame difference for the first macro block. The second processor executes a discrete cosine transform for the first macro block, a quantization for the first macro block, an inverse quantization for the first macro block, an inverse discrete cosine transform for the first macro block and a loop filtering for the second macro block. The motion vector detection and the discrete cosine transform are concurrently processed and the inter-frame addition and the loop filtering are concurrently processed, thereby the processing times for each macro block are shortened and thus a high speed processing is realized.

Motion picture coder and system for controlling the same

For improvement in processing speed, a high-speed digital signal processor has a feedback loop from a register which stores the calculating result produced by a Signed Digit (SD) arithmetic unit to one of the input ports of the SD arithmetic unit. The SD arithmetic unit executes an arithmetic operation on an input digital signal and the arithmetic result is formed of both signed digit numbers without the need to convert the calculation result represented by an SD number into a binary number.

High speed digital signal processor for signed digit numbers

An arithmetic circuit has a first subtracter receiving first and second input signals which are composed of a plurality of bits and operative to output a first output signal representative of the first input signal minus the second input signal, and a second subtracter receiving the first and second input signals so as to output a second output signal representative of the second input signal minus the first input signal. A selector receives the first and second output signals and operates in response to one of the first and second output signals so as to alternately output the first and second output signals.

Arithmetic circuit for calculating the absolute value of the difference

A process of fabricating a three-dimensional semiconductor device, comprising the steps of preparing at least two multilayer structures each including at least one semiconductor element and a conductor connected at one end to the semiconductor element and having at the other end an exposed surface, at least one of the multilayer structures further including a thermally fusible insulating adhesive layer having a surface coplanar with the exposed surface of the conductor, positioning the multilayer structures so that the exposed surfaces of the respective conductors of the multilayer structures are spaced apart from and aligned with each other, moving at least one of the multilayer structures with respect to the other until the exposed surfaces of the conductors of the multilayer structures contact each other, and heating the multilayer structures for causing the insulating adhesive layer of at least one of the multilayer structures to thermally fuse to the other multilayer structure with the semiconductor elements electrically connected together.

Growing community of inventors

Tokyo, Japan

Tadayoshi Enomoto