Micron Technology Incorporated

Ulvac, Inc.

Tadashi Yamamoto

Yutaka Ito

Kang-Yong Kim

Huy Thanh Vo

Zer Liang

Jacob Robert Anderson

Kazumasa Horita

Takahiko Sawada

Hyung-Woo Ahn

A method of manufacturing an OTS device of the invention is a method of manufacturing OTS device including a first conductor, an OTS portion made of chalcogenide, and a second conductor which are layered in order and disposed on an insulating substrate. The manufacturing method includes: a step D of forming a resist so as to coat part of an upper surface of the second conductor; a step E of dry etching a region which is not coated with the resist; and a step F of ashing the resist. In the step E, the second conductor, all of the OTS portion, and an upper portion of the first conductor are removed by an etching treatment once in a depth direction of the region.

Method of manufacturing OTS device, and OTS device

Various embodiments comprise apparatuses to assign unique device identifier values to addressable devices in a stacked package. In one embodiment, an apparatus is disclosed including a stacked package with at least two addressable devices. Each of the addressable devices includes data input and switch path circuitry, a shift register coupled to the data input and switch path circuitry, and a single through-substrate via (TSV) through which the unique device identifier values can be assigned. The single TSV is coupled to the data input and switch path circuitry and between adjacent ones of the at least two addressable devices. Additional apparatuses, systems, and methods are described.

Identifying stacked dice

Memories containing command decoder, chip enable, and signal truncation circuits are disclosed. One such command decoder circuit may include command decoder logic configured to receive command signals and output a decoded command to an interconnect bus responsive to a chip select signal having an active state. Decoder circuits may also prevent coupling commands to the interconnect bus based on the receipt of chip select signals having inactive states. Chip enable circuits having control logic are configured to receive chip select signals and provide the chip select signals to an interconnect bus responsive to receiving a valid command. Chip enable circuits may also prevent coupling chip select signals to the interconnect bus from chip enable signals based on the receipt of invalid command signals. Signal truncation circuits may be used to shorten and/or shift chip select signals to increase timing margins and improve the reliability of command execution by memories.

Method and apparatus for memory command input and control

Memories containing command decoder, chip enable, and signal truncation circuits are disclosed. One such command decoder circuit may include command decoder logic configured to receive command signals and output a decoded command to an interconnect bus responsive to a chip select signal having an active state. Decoder circuits may also prevent coupling commands to the interconnect bus based on the receipt of chip select signals having inactive states. The memory further may include chip enable circuits having control logic configured to receive chip select signals and provide the chip select signals to an interconnect bus responsive to receiving a valid command. Chip enable circuits may also prevent coupling chip select signals to the interconnect bus from chip enable signals based on the receipt of invalid command signals. Signal truncation circuits may be used to shorten and/or shift chip select signals to increase timing margins and improve the reliability of command execution by memories.

Apparatus, systems, and methods are disclosed that operate within a memory to execute internal commands, to suspend the execution of commands during a transfer period, and to execute external commands following the transfer period. Additional apparatus, systems, and methods are disclosed.

Command interface systems and methods

A method for manufacturing a magnetic device that obtains sufficient processing accuracy without increasing mask removal steps. A first mask layer is formed above a magnetic layer using one selected from the group consisting of Ti, Ta, W, and an oxide or a nitride thereof. A second mask layer is formed on the first mask layer using Ru or Cr. A resist pattern is formed on the second mask layer. A second mask pattern is formed by performing reactive ion etching with reactive gas containing oxygen on the second mask layer using the resist pattern. A first mask pattern is formed by performing reactive ion etching with reactive gas containing halogen gas on the first mask layer using the second mask pattern. A magnetic pattern is formed by performing reactive ion etching with reactive gas containing oxygen on the magnetic layer using the first mask pattern.

Growing community of inventors

Ibaraki, Japan

Tadashi Yamamoto