Nippondenso Co., Ltd.

Tadashi Shibata

Takamoto Watanabe

Shigenori Yamauchi

Yoshinori Fujihashi

Satoshi Suzuki

Shoji Miura

Toshio Sakakibara

Makio Iida

Takayuki Sugisaka

Hajime Nomura

Toshio Ikuta

Hiroyuki Kano

Yoshinori Gotoh

Hirofumi Abe

Kenji Murakami

Shunji Kamei

Takatoshi Kato

Masanori Usui

A frequency multiplying device which multiplies the frequency of an externally-supplied reference signal PREF includes a digitally-controlled oscillation circuit, which includes a ring oscillator formed of thirty-two inverting circuits in a ring configuration which are adapted to generate sixteen clock signals having a period that is thirty-two times the inversion time of each inverting circuit and a phase interval that is twice the inverting circuit inversion time, and produces an output signal POUT having a period that corresponds to frequency control data CD at a resolution of the phase difference time of the clock signals, a counter/data-latch circuit which counts the clock signal RCK released by the ring oscillator within one period of the reference signal PREF and delivers the frequency control data CD of the count value to the digital oscillation circuit, and a control circuit which controls the operation of the circuits so that the oscillation output signal POUT having the frequency of the reference signal PREF multiplied by sixteen (32/2) is generated by the digital oscillation circuit.

Frequency multiplying device and digitally-controlled oscillator

A transistor T26, serving as an output circuit 42, has a collector connected to a communication line B+ and an emitter connected to the other communication line B-. A base current generation circuit 44 generates a base current Ib for actuating transistor T26 based on a transmission signal. Transistors T24 and T25 constitute a current-mirror circuit. A correction circuit 46 takes in or absorbs a current equivalent to base current Ib from the collector of transistor T26, so as to equalize the drive currents IB+ and IB- flowing through twin communication lines B+ and B-. Since only one transistor T26 is used to actuate the twin communication lines B+ and B-, it, becomes possible to completely equalize the drive currents IB+ and IB- in their absolute values and to cause no phase dislocation between these two drive currents IB+ and IB-. Hence, the radio noises can be completely canceled when generated from each of twin communication lines B+ and B- due to change of currents flowing therethrough.

Driver circuit arrangement used in a local area network

A compact input/output processing IC, which reduces the CPU load, to which microcomputer 100, input/output processing IC 200, and various inputs and outputs are connected. Parallel signals are connected to a high-speed input/output buffer and serial signals are connected from communications control circuit 207 via serial communications circuit 206 to SIO 104. To achieve the proper control, data requiring high speed is handled by parallel communications. Serial communications is handled by shift registers, first bit of each being connected to the last bit of the other, to form a loop, with instruction and input/output data from the CPU exchanged simultaneously, thereby achieving efficient processing. This achieves better organization of the communications for input/output processing, enabling both better control and a compact hardware design.

Input/output processing IC

A semiconductor device is provided which makes a high withstand voltage bipolar transistor small and prevents deterioration in a switching speed of the transistor. A silicon oxide layer is formed on a silicon substrate, and a semiconductor island of one conductivity type which is isolated laterally by an isolation trench is formed on the silicon oxide layer. A silicon oxide film is formed on an outer periphery portion of the semiconductor island to bury the trench. In the semiconductor island, a bipolar transistor, namely a base region of the other conductivity type, is formed, and in the base region an emitter region of one conductivity type is formed and a collector region of one conductivity type is further formed. In the semiconductor island a diffusion region of the other conductivity type for extracting excessive carriers to which a constant electric potential is applied is further formed.

Dielectric isolated type semiconductor device provided with bipolar

A field-effect transistor includes a semi-insulating substrate, a semiconductor layer consisting of successive layers of GaAs compound semiconductor formed on the substrate, a gate electrode forming a Schottky contact with the semiconductor layer, and source and drain electrodes each forming an ohmic contact to the semiconductor layer. A semiconductor layer includes a buffer layer, an active layer, and a contact layer, where the impurity concentration in the contact layer is substantially equal to that in the active layer at the interface therewith. The impurity concentration in the contact layer increases continuously from the interface toward the upper surface of the contact layer. The field-effect transistor achieves a reduction in the ON resistance and an increase in the gate breakdown voltage at the same time, and to reduce power loss and increase efficiency.

Field-effect transistor having a graded contact layer

A semiconductor sensor device which has a decreased number of terminals, which is cheaply and compactly constructed and which contains a trimming circuit. A power source voltage and a clock signal having a voltage level greater than the power source voltage are input to a terminal 31. A logic circuit 22 starts operating at one voltage level of a terminal 33 and temporarily stores serial digital signals that are input through a terminal 32 in response to clock signals as parallel trimming data. A gauge circuit 11 operates based on the stored trimming data, and the gauge output is sent to the terminal 32. With another voltage level from the terminal 33, the logic circuit 22 trims a fuse memory circuit 23 based on the stored trimming data. At a further voltage level from the terminal 33, the gauge circuit 11 is operated based on the data in the fuse memory circuit 23 that is trimmed, and an output signal thereof is sent to the terminal 32.

Semiconductor sensor device

A programmable semiconductor memory cell is provided; which secures a sufficient output signal voltage margin and which also has reduced current dissipation and improved durability. To program the programmable semiconductor memory cell of this invention, a high write potential is applied to the high-level lead of a fuse and a selector transistor is turned on to blow the fuse. When reading the memory cell, high read potential is applied to the high-level lead of the fuse. Because an emitter and base of an output transistor are connected to both leads of the fuse, the output transistor is turned on when the fuse is blown and is turned off when the fuse is not blown. The output transistor outputs an amplified signal voltage to an output line.

Growing community of inventors

Toyokawa, Japan

Tadashi Shibata