Other

Canon Kabushiki Kaisha

Bridgestone Corporation

Tadashi Shibata

Rohm Co., Ltd.

Semiconductor Technology Academic Research Center

Tadahiro Ohmi

Tadashi Shibata and Tadahiro Ohmi

Adv Antest Corporation

Tohoku University

Frontec Incorporated

Kabushiki Kaisha Ultraclean Technology Research Institute

Takasago Netsugaku Kogyo Kabushiki Kaisha

Applied Materials Japan Inc.

I & F, Inc.

Masaru Umeda

Koji Kotani

Katsuhisa Ogawa

Takeo Yamashita

Takahisa Nitta

Masahiro Konda

Ryota Fujio

Tatsuo Morimoto

Makoto Imai

Toshiyuki Nozawa

Yuichiro Yamashita

Makoto Ogawa

Atsushi Yamagami

Takashi Imaoka

Nobuyuki Okamura

Masakazu Nakamura

Hisayuki Shimada

Akira Nakada

Mizuho Morita

Hidetoshi Wakamatsu

Masanori Fujibayashi

Nobuhiro Konishi

Haruhiro Harry Goto

Rita Wai-Chi Au

Jinzo Watanabe

Shintaro Aoyama

Eiji Nakamura

Hirofumi Aoki

Akira Nakano

Hideo Takeichi

Koichi Morita

Hiroaki Terada

Masayuki Ohashi

Kazuyuki Maruo

Michiya Kawakami

Hideaki Yokoyama

Ryu Kaiwara

Toshiyuki Ishikuro

Keng Hoong Wee

Takemi Yonezawa

Kiyoto Ito

Masahiro Konnda

Akira Nataka

Tadhiro Ohmi

Kazuhisa Miyashita

Hiroaki Uetake

Hideo Kosaka

Tsutomu Nakai

Ning Mei Yu

Tatsuro Morimoto

The present invention relates to a tire having as a member, a rubber composition comprising (a) 100 mass parts of a rubber component comprising at least one selected from a natural rubber and a diene base synthetic rubber, (b) silica having a nitrogen-absorbing specific surface area (N2SA) of 180 to 270 m2/g and 0.1 to 10.0 mass parts of (c) a partial ester compound of maleic anhydride and a (poly)oxypropylene derivative described above. The tire further comprises as a tread rubber, a rubber composition comprising (A) a rubber component comprising a conjugate diene base rubber, (B) a filler comprising 10 mass % or more of a white filler based on the whole fillers and (C) a partial ester compound of maleic anhydride and a (poly)oxypropylene derivative. This tire has good abrasion resistance, enhanced low heat build-up property, improved processability, excellent driving stability, good physical properties and excellent wet gripping property.

Tire

There is provided a rubber composition for a tread obtained by compounding (a) 5-40 parts by mass of a softening agent including an oil in which an extraction quantity with dimethylsulfoxide (DMSO) by IP346 process is controlled to less than 3% by mass and (b) 5-40 parts by mass of a liquid polymer having a viscosity average molecular weight of 45,000-100,000 based on 100 parts by mass of a rubber component, and considerably improving the fracture properties and wear resistance and controlling the lowering of the modulus of elasticity as compared with the case of compounding the conventional high aromatic oil.

Rubber composition for tread and tire

SRAMs A, B, C, and D having pixel data of each small block of each large block, for example a small block Afor the SRAM A, to simultaneously read out a plurality of pixel data in the small block by specifying an address assigned to each small block, and a matrix of coefficient in which a matrix of plural coefficients are arranged are provided. Also provided are a coefficient matrix controllerand an adding sectionto multiply the plural coefficients respectively by pixel data corresponding to each thereof and obtain a sum of the multiplied results. Each pixel data of each small block forming one large block, the pixel data being read out from the SRAMs A, B, C, and D, are multiplied by the coefficient matrix rearranged into a predetermined order.

Image processing device and image processing method

There is provided a semiconductor circuit including three or more nodes at least including one input node and one output node, plural paths which are connected between the three or more nodes and whose signal propagation directions between the nodes are regulated, a signal propagation time regulator for regulating a signal propagation time of each of the paths, an input unit for inputting a predetermined input signal to the input node, and a detector for detecting a time required for the input signal to propagate through the paths and arrive at the output node.

Semiconductor circuit for detecting a signal propagation time

There is provided a semiconductor circuit for arithmetic processing and an arithmetic processing method that can increase the rate of processing data and reduces the area of a circuit by suppressing wasteful processing. There is provided a computing unit for computing input data, and this computing unit computes input digit data within a computation time unit and outputs a computation result representing a result obtained by the computation, and if a carry is generated in the computation a computation circuit (adders) for outputting carry data representing this carry, and delay means (memory) for delaying the computation result from the computation circuit by one computation time unit, are provided.

Semiconductor circuit for arithmetic processing and arithmetic processing method

A method of forming an oxide film having high insularity capability is performed within an ultra clean environment, using charged particles.

Oxide film forming method

There is provided a semiconductor circuit for arithmetic processing and an arithmetic processing method that can increase the rate of processing data and reduces the area of a circuit by suppressing wasteful processing. There is provided a computing unit for computing input data within a computation time unit and outputs a computation result representing a result obtained by the computation, and if a carry is generated in the computation a computation circuit (adders ) for outputting carry data representing this carry, and delay means (memory ) for delaying the computation result from the computation circuit by one computation time unit, are provided.

Semiconductor circuit for arithmetic operation and method of arithmetic operation

A semiconductor arithmetic unit which realizes a maximum or minimum value retrieval operation at high speed and with a high degree of accuracy used in a vector quantization processor is composed of a binary-multivalue-analog merged operation processing circuit. A multi-loop circuit includes an amplifying circuit group composed of a plurality of sets of first amplifiers with a floating gate to which first electrodes and a single second electrode are capacitively coupled with a predetermined ratio, a logical operation circuit to which output signals of the amplifying circuit group are inputted and which outputs a logical 0 or 1, and a second amplifying circuit to which an output signal of the logical operation circuit is inputted and whose output is distributed to all of the second electrodes of the amplifying circuit group. The second amplifying circuit includes an adjusting circuit which adjusts an output current driving ability and a controlling circuit which controls the adjustment with a predetermined regulation. The adjustment of the controlling circuit is executed according to variation of the output of the logical operation circuit.

Semiconductor arithmetic unit

A computing circuit capable of computing an absolute difference with high-speed analog computation, a computing apparatus capable of computing the sum of absolute differences and a semiconductor computing circuit achievable with simple circuitry and suitable for use in such a computing circuit or apparatus. The computing circuit capable of computing the absolute difference includes a large input selection circuit which outputs either a first signal or a second signal whichever is larger, a small input selection circuit which outputs either the first and second signals whichever signal is smaller, and a subtraction circuit which subtracts the output of the small input selection circuit from the output of the large input selection circuit The subtraction circuit includes a capacitor a first switch provided between a first terminal of the capacitor and the output of the large input selection circuit a second switch provided between the first terminal of the capacitor and the output of the small input selection circuit and a third switch provided between a second terminal of the capacitor and a terminal connected to a prescribed potential. The computing apparatus capable of computing the sum of absolute differences includes a plurality of such computing circuits, and computes the sum of the outputs of the computing circuits by using a summing circuit.

Computing circuit, computing apparatus, and semiconductor computing circuit

A sum of product circuit ( ) which adds up two input voltages, each of which is multiplied by the prescribed coefficients. The sum of product circuit ( ) has a &ngr; MOS transistor ( ), a first and a second capacitance (C , C ), and an output terminal ( ). The &ngr; MOS transistor ( ) includes a drain ( ), source ( ), and a floating gate ( ). The first and a second capacitance (C , C ) connects each of two input voltages to the floating gate ( ) by capacity coupling. The output terminal ( ) outputs a voltage realized between a resister element (R ) and the &ngr; MOS transistor ( ). A constant voltage is applied between the drain ( ) and the source ( ) through the resister element (R ).

Sum of product circuit and inclination detecting apparatus

The present invention has as an object thereof to provide a semiconductor arithmetic circuit which is capable of conducting edge accentuation processing, edge detection processing, and noise removal by means of averaging processing of an image, using extremely simple circuitry. A semiconductor arithmetic circuit is provided with an amplifier circuit in which an input terminal is connected to the gate electrode of at least one MOS type transistor, a first signal input terminal, which is connected with the input terminal via a first switching element, and a plurality of second signal input terminals, which are connected with the input terminal via a capacity element; wherein a mechanism is provided for opening the first switching element in a state in which a first signal voltage is applied to the input terminal and a predetermined second input signal voltage group is applied to the second signal input terminals, and for thereafter applying a predetermined third input signal voltage group to the second signal input terminals, and wherein the amplifier circuit comprises a source follower circuit or a voltage follower circuit.

Semiconductor arithmetic circuit

Disclosed is a semiconductor computing circuit achievable with simple circuitry and capable of performing analog computations at high speed to compute an absolute-value voltage representing the difference between a first signal voltage and a second signal voltage. The semiconductor computing circuit comprises: a first MOS transistor having a floating gate and a control gate capacitively coupled to the floating gate; a second MOS transistor having a floating gate and a control gate capacitively coupled to the floating gate, and whose source electrode is connected to the source electrode of the first MOS transistor; a write circuit which, with a prescribed voltage applied to the control gates of the first and second MOS transistors, sets the potential at the floating gate of the first MOS transistor to a value equal to the first signal voltage and also sets the potential at the floating gate of the second MOS transistor equal to a value obtained by subtracting the first signal voltage from the prescribed voltage; and a difference voltage computing circuit for computing a voltage representing a value obtained by subtracting the second signal voltage from the prescribed voltage, and wherein: after setting the first and second MOS transistors by the write circuit, when the output voltage of the difference voltage computing circuit is applied to the control gate of the first MOS transistor while at the same time applying the second signal voltage to the control gate of the second MOS transistor, the absolute-value voltage representing the difference between the first signal voltage and the second signal voltage is output.

Semiconductor computing circuit and computing apparatus

The problem of increase in jitter amounts against increase in delay amounts is solved by a circuit wherein a signal input terminal is connected through a first capacitor to an input terminal of a sense amplifier, a control input terminal is connected through a second capacitor to the input terminal of the sense amplifier, and a common connection point between the input terminal of the sense amplifier and the first and second capacitors is a floating node, and wherein a signal applied through the signal input terminal to the input terminal of the sense amplifier is vertically shifted by a control signal applied to the control input terminal, at least, near a determination threshold of the sense amplifier, thereby controlling a delay amount of an output.

Semiconductor integrated circuit, delay-locked loop having the same circuit, self-synchronizing pipeline type system, voltage-controlled oscillator, and phase-locked loop

The present invention is intended to provide a semiconductor memory circuit that can store analog and many-valued data at high speed and with a high degree of accuracy. The semiconductor memory circuit comprises a memory cell in which analog and many-valued signals can be written and stored, a readout circuit having an output terminal which outputs the values stored in the memory cell to the outside as voltages, a comparator having an output terminal which outputs a write end signal when the output terminal voltage of the readout circuit equals to a predetermined voltage, a write voltage controlling circuit having an output terminal which outputs an output voltage corresponding to the analog and many-valued voltage values inputted to an input terminal as a writing voltage of the memory cell, and a write voltage switching circuit having a function which supplies the output voltage of the write voltage controlling circuit to the memory cell and stops to supply the output voltage of the write voltage controlling circuit to the memory cell when the write end signal is outputted to the output terminal of the comparator.

Semiconductor memory device

Growing community of inventors

Tokyo, Japan

Tadashi Shibata