Kabushiki Kaisha Toshiba

Sony Corporation

Sumitomo Electric Device Innovations, Inc.

Kioxia Corporation

Tadashi Sakai

Naoshi Sakuma

Yuichi Yamazaki

Mariko Suzuki

Masayuki Katagiri

Tomio Ono

Akihiro Kajita

Makoto Wada

Hisao Miyazaki

Tatsuro Saito

Masayuki Kitamura

Atsunobu Isobayashi

Atsuko Sakata

Hiroaki Yoshida

Li Zhang

Kazuya Nakayama

Taishi Ishikura

Ichiro Mizushima

Shigeki Uno

Hideyuki Funaki

Yasutaka Nishida

Masayuki Nakamoto

Moriyasu Ichino

Takeshi Sawada

Masaki Katsura

Takashi Yoshida

Taketoshi Suzuki

Zhang Li

Akio Nakagawa

Kazuhiro Suzuki

Takashi Shinohe

Ichiro Omura

Toru Tanaka

Tetsufumi Tanamoto

Yoshinori Iida

Shigeki Takahashi

Kazuyoshi Furukawa

Chiharu Ota

Kazuto Takao

Hiromichi Ohashi

Ikuo Fujiwara

Isao Amemiya

Keitaro Shigenaka

Takashi Yamauchi

Masao Koyama

Gehan Anil Joseph Amaratunga

Masamichi Ippommatsu

Hitoshi Yagi

Masayuki Sekimura

Riichi Katoh

Masayuki Shiratori

Yujiro Naruse

Masaru Shimbo

Osamu Takikawa

Hideaki Hiraki

Ryuji Oki

Nanao Nakamura

Isamu Yanase

Toru Ukai

Taijun Murakami

Ioannis Alexandrou

Shintaro Sato

Naohsi Sakuma

Nalin Rupasinghe

Mark Baxendale

Toshimi Kikuchi

Harutoshi Egami

Eikichi Ichimori

A laminated body of an embodiment includes: a silicon layer; a first beryllium oxide layer on the silicon layer; and a diamond semiconductor layer on the first beryllium oxide layer.

Laminated body and semiconductor device

According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.

Method for manufacturing a semiconductor device

A graphene wiring structure of an embodiment has: an amorphous or polycrystalline insulating film; and a multilayer graphene on the insulating film. The multilayer graphene including a plurality of graphene crystals having a zigzag direction is oriented at 17 degrees or less with respect to an electric conduction direction on the insulating film.

Method for manufacturing graphene wiring structure and method for manufacturing wiring structure

Graphene wiring structure and semiconductor device using the same

Provided is a semiconductor device according to an embodiment including an i-type or first-conductivity-type first diamond semiconductor layer having a first side surface, a second-conductivity-type second diamond semiconductor layer provided on the first diamond semiconductor layer and having a second side surface, a third diamond semiconductor layer being in contact with the first side surface and the second side surface, the third diamond semiconductor containing nitrogen, a first electrode electrically connected to the first diamond semiconductor layer, and a second electrode electrically connected to the second diamond semiconductor layer.

Semiconductor device

In one embodiment, a diamond semiconductor device includes a first diamond semiconductor layer of a first conductivity type which has a main surface, a second diamond semiconductor layer of an i-type or a second conductivity type which is provided on the main surface of the first diamond semiconductor layer, and has a first side surface with a plane orientation of a {111} plane, a third diamond semiconductor layer of the first conductivity type which is provided on the first side surface, and a fourth diamond semiconductor layer of the second conductivity type which is provided on the main surface of the first diamond semiconductor layer and on a side surface of the second diamond semiconductor layer at a side opposite to a side of the third diamond semiconductor layer.

Diamond semiconductor device

A semiconductor device according to an embodiment includes an i-type or a p-type first diamond semiconductor layer, an n-type second diamond semiconductor layer provided on the first diamond semiconductor layer, a mesa structure and an n-type first diamond semiconductor region provided on the side surface. The mesa structure includes the first diamond semiconductor layer, the second diamond semiconductor layer, a top surface with a plane orientation of &#xb1;10 degrees or less from a {100} plane, and a side surface inclined by 20 to 90 degrees with respect to a direction of &#x3c;011&#x3e;&#xb1;20 degrees from the {100} plane. The first diamond semiconductor region is in contact with the second diamond semiconductor layer and has an n-type impurity concentration lower than an n-type impurity concentration of the second diamond semiconductor layer.

Semiconductor device and method of manufacturing the same

A graphene wiring structure of an embodiment has a multilayered graphene having a plurality of planar graphene sheets laminated, and a first interlayer substance being a metal oxyhalide between the plurality of planar graphene sheets.

Graphene wiring structure and method for manufacturing graphene wiring structure

A graphene wiring structure of an embodiment has a substrate, a metal part on the substrate, multilayered graphene connected to the metal part, a first insulative film on the substrate, and a second insulative film on the substrate. The metal part is present between the first insulative film and the second insulative film. Edges of the multilayered graphene are connected to the metal part. A side face of the first insulative film vertical to the substrate opposes a side face of the second insulative film vertical to the substrate. A first outer face of the multilayered graphene is in physical contact with a first side face of the first insulative film vertical to the substrate. A second outer face of the multilayered graphene is in physical contact with a second side face of the second insulative film vertical to the substrate.

According to one embodiment, a semiconductor device is disclosed. The device includes a graphene layer containing impurities, and including a first region and a second region. The second region has a resistance higher than a resistance of the first region. The second region includes a side surface of an end of the graphene layer. The device further includes a first plug being in contact with the first region.

Semiconductor device and manufacturing method thereof

A semiconductor device of an embodiment includes a layered substance formed by laminating two-dimensional substances in two or more layers. The layered substance includes at least either one of a p-type region having a first intercalation substance between layers of the layered substance and an n-type region having a second intercalation substance between layers of the layered substance. The layered substance includes a conductive region that is adjacent to at least either one of the p-type region and the n-type region. The conductive region includes neither the first intercalation substance nor the second intercalation substance. A sealing member is formed on the conductive region, or on the conductive region and an end of the layered substance.

Semiconductor device, superconducting device, and manufacturing method of semiconductor device

Graphene wiring of an embodiment has a graphene intercalation compound including a multilayer graphene having graphene sheets stacked therein and an interlayer substance disposed between layers of the multilayer graphene, and an interlayer cross-linked layer connected to a side surface of the multilayer graphene. The interlayer cross-linked layer has a cross-linked molecular structure including multiple bonded molecules cross-linking the graphene sheets included in the multilayer graphene.

Graphene wiring and method for manufacturing the same

According to one embodiment, a semiconductor device is disclosed. The device includes interconnects each including a catalyst layer and a graphene layer thereon. The catalyst layer includes a first to fifth catalyst regions arranged along a first direction in order of the first to fifth catalyst regions. The first, third and fifth catalyst regions include upper surfaces higher than those of the second and fourth catalyst regions. Adjacent ones of the first to fifth catalyst regions are in contact with each other. A distance between the first and the third catalyst region and a distance between the third and fifth catalyst region are greater than a mean free path of graphene. The graphene layer includes a first graphene layer on the second catalyst region and a second graphene layer on the fourth catalyst region.

According to one embodiment, a semiconductor device includes an underlayer formed on a substrate, a catalyst layer disposed on the underlayer and extending in an interconnect length direction. The device further includes an upper graphene layer formed on an upper face of the catalyst layer, and side graphene layers provided on two respective side faces of the catalyst layer, the two side faces extending in the interconnect length direction.

Growing community of inventors

Yokohama, Japan

Tadashi Sakai