Fujitsu Corporation

Fujitsu Microcomputer Systems Limited

Fujitsu Micromputer Systems Limited

Fujitsu Limited & Fujitsu Microcomputer Systems Ltd.

Tadashi Saitoh

Takayoshi Taniai

Yasuhiro Tanaka

Hidetoshi Shimura

Hajime Sato

Atsushi Fujihira

Shinji Oyamada

Hajime Satoh

A data processing device contains art execution circuit and a data buffer circuit which stores one or more commands and/or one or more parameters which are prefetched, until each of the commands and parameters is read out by the execution circuit. The execution circuit inputs the oldest command stored in the data buffer circuit when an execution of a preceding command is completed, inputs one or more parameters stored in the data buffer circuit when the command input therein requests the parameters, and executes the command input therein, using the parameters when the parameters are input therein. The device further contains a circuit for detecting whether or not there is enough vacant space in the data buffer circuit in which a further command and/or a parameter can be stored, and another circuit for detecting a state of the data buffer circuit in which state the data buffer circuit does not store data including a command and/or a parameter, which is necessary for a next operation in the execution circuit. A prefetch control circuit, provided in either in the device or outside of the device, starts the prefetch operation and continues successive prefetch operations when the second state is detected, and stops the prefetch operation when the first state is detected. The system using the device contains a memory which stores the commands and parameters in the order of execution in the execution circuit.

System and device for prefetching command and parameters to be processed

A data control device which acquires the right to use a bus and performs data control includes a request circuit which selectively generates a plurality of request signals for acquiring the right to use corresponding buses. The plurality of request signals are based on attributes of data to be exchanged with an external device. The exchanged data includes data and commands.

Data control device generating different types of bus requests and

A direct memory access controller coupled to a system bus of a system for controlling data transfers through a channel includes the following. A request handler receives a transfer request generated by a device connected to the system bus. A transfer control information register stores transfer control information used for obtaining transfer control information necessary for executing the data transfer by a next transfer request supplied from the request handler. A temporary register stores the transfer control information necessary for processing the next transfer request. A transfer control information setting circuit generates the transfer control information necessary for processing the next transfer request on the basis of the transfer control information registered in the transfer control information register during the data transfer by the present transfer request and then renewing the transfer control information and-temporary registers with the generated transfer control information. A transfer execution circuit executes the actual data transfer through the system bus in accordance with the transfer control information registered in the temporary register, which is output to the system bus therefrom.

Direct memory access controller for handling cyclic execution of data

A direct memory access controller coupled to a system bus for controlling a data transfer by a direct memory access comprises an internal bus, a data handler coupled to the system data bus and the internal bus for controlling an exchange of data between the system bus and the internal bus, a microsequencer which controls by microprograms parts of the direct memory access controller in units of one system clock cycle during one present transfer cycle, and a programmable logic array part supplied with a transfer request, a transfer mode information and at least portions of a transfer address and a byte count. The programmable logic array part is coupled to the internal bus and outputs control information required during a next transfer cycle during one transfer cycle which corresponds to a predetermined number of system clock cycles. Each data transfer between the input/output device and the memory device is controlled by the microprograms of the microsequencer in cooperation with the programmable logic array part.

DMA controller having programmable logic array for outputting control

A data transfer control system controls a data transfer between a source and a destination by rearranging a data arrangement of a data which is made up of data units each made up of one or a plurality of bits, and comprises an input/output interface unit for inputting the data from the source and for outputting the data to the destination, a data swap circuit coupled to the input/output interface unit for rearranging a data arrangement of the data received from the source through the input/output interface unit in terms of the data unit and for rearranging a data arrangement of the data outputted to the destination through the input/output interface unit in terms of the data unit, a temporary register for temporarily storing the data with the rearranged data arrangement obtained from the data swap circuit, and a data swap control circuit coupled to the data swap circuit for controlling the rearranging of the data arrangement in the data swap circuit responsive to a transfer information which includes at least a source address, a destination address and a transfer control information.

Data transfer system for rearranging data units using intermediate

A programmable logic array includes a programmable logic array being precharged and discharged in synchronism with a clock signal supplied thereto and outputting an operation result with respect to input data supplied thereto. The programmable logic array also includes a circuit connected to the programmable logic array, for holding the programmable logic array in a precharged state by setting the clock signal to a fixed level when the programmable logic array is not selected and for switching the programmable logic array to a discharged state by supplying the clock signal the programmable logic array when the programmable logic array is selected, so that the programmable logic array is discharged on the basis of the contents of the input data when selected.

Programmable logic array with reduced power consumption

A data transfer controlling apparatus for direct memory access comprising one or more first microaddress registers, each of which registers stores microaddress information for program processing of the data transfer for a corresponding channel; a second microaddress register which stores microaddress information for program processing other than the program processing of the data transfer; a micro read only memory operatively connected to said first and second microaddress registers, for storing microinstructions and outputting a predetermined microinstruction in accordance with microaddress information read out from a selected one of the first microaddress registers and the second microaddress register; and an incremental element operatively connected to said first and second microaddress registers, for incrementing the value of the microaddress information read out from the selected one of the first microaddress registers and the second microaddress register, and for writing the incremented microaddress information to the selected one of the first microaddress registers and the second microaddress register; the microaddress information stored in one of the first microaddress registers for the corresponding channel being read out when program processing of data transfer for the corresponding channel is carried out, the microaddress information stored in the second microaddress register being read out when program processing other than the program processing of data transfer is carried out.

Data transfer controlling apparatus for direct memory access

A semiconductor integrated circuit comprises an internal data bus, a first holding part for entering and holding data which are obtained from outside the semiconductor integrated circuit via the internal data bus, a reading part for reading out the data held in the first holding part and for outputting the read out data to the internal data bus, a second holding part for entering and holding the data which is read out by the reading part via the internal data bus, a third holding part for entering and holding test data which are obtained from outside the semiconductor integrated circuit bia the internal data bus, a discriminating part for comparing the data held in the second and third holding part and for obtaining a discrimination result based on whether the compared data coincide, and an output part for outputtting the discrimination result of the discrimination part of the outside of the semiconductor integrated circuit.

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Kawasaki, Japan

Tadashi Saitoh