Nec Corporation

Mitsubishi Electric Corporation

Dynamic Map Platform Co., Ltd.

Tadashi Ozawa

Tsutomu Nakajima

Toshiharu Suzuki

Kenji Togashi

A three-dimensional map generation system () generates three-dimensional map information () by using measured data acquired by a measurement vehicle () moving in a measurement area (). A determination unit () determines, from the measurement area (), a data shortage area where measured data for generating the three-dimensional map falls short, based on first measured data () transmitted from the measurement vehicle (). A generation unit () generates interpolated data which interpolates three-dimensional map information of a defective area with a NURBS curve so that a lateral G, which is centrifugal force in a lateral direction applied to a traveling vehicle traveling a road in the defective area at a traveling speed, is equal to or less than a predefined threshold ().

Three-dimensional map generation system, three-dimensional map generation method, and computer readable medium

A thermal resistance variable heat sink structure is provided that can improve the quality during operation and that can change the shape of a heat sink and reduce the number of steps attaching and detaching. Solder balls are disposed for connection of a LSI . A mounting plate on which a heat sink is mounted, screws for mounting the heat sink, a radiation fin , and a thermal resistance adjuster are disposed on the back surface of the LSI . The thermal resistance adjuster is placed on the middle of the back surface to cut the cooling air.

Thermal-resistance variable heat sink structure and method of using the same

In a failure analysis method for a ball grid array type semiconductor device including a semiconductor chip having pads, first solder balls, an interposer substrate and second solder balls, the second solder balls and the interposer substrate are removed from the semiconductor device, and then, the first solder balls are removed from the semiconductor device. Then, the semiconductor device is mounted on a package, and a wire bonding operation is performed between the pads of the semiconductor chip and bonding pads of the package. Finally, a test operation is performed upon the semiconductor chip by mounting the package on a tester.

Failure analysis method for chip of ball grid array type semiconductor device

A semiconductor device comprises a semiconductor substrate of a first conductivity type; an epitaxial layer of a second conductivity type formed on the semiconductor substrate; an impurity diffusion layer of the second conductivity type embedded between the semiconductor substrate and the epitaxial layer and having an impurity concentration greater than that of the epitaxial layer; a resistance region reaching the impurity diffusion layer from a surface of the epitaxial layer and extending substantially vertically to the surface of the epitaxial layer; an insulating film defining the resistance region; and a lead region selectively formed between the surface of the epitaxial layer and the impurity diffusion layer.

Growing community of inventors

Tokyo, Japan

Tadashi Ozawa