Elpida Memory, Inc.

Nec Corporation

Tadashi Onodera

Kazuhiko Kajigaya

Hitoshi Tanaka

Yoshinori Matsui

Akiyoshi Yamamoto

Hideo Inaba

A semiconductor device includes: first and second input/output terminals; a first input/output line connected to the first input/output terminal; a second input/output line connected to the second input/output terminal; and a first by-path route that connects the first input/output line and the second input/output line. When in normal operation mode, the first by-path route is set in a non-conductive state. When in a test mode, the first by-path route is set into a conductive state so that a first data inputted to the first input/output terminal is outputted as a first data to the second input/output line, in correspondence with a transition of a clock signal in the first direction, and so that a second data inputted to said first input/output terminal is outputted as a second input data for said first input/output line, in correspondence with a transition of said clock signal in the second direction.

Semiconductor device testable on quality of multiple memory cells in parallel and testing method of the same

A self-refresh timer circuit for generating a timer period for controlling self-refresh operation of a semiconductor memory device comprising: a temperature-dependent voltage source for outputting a voltage having a temperature dependency based on a diode characteristic; a control current generating circuit for applying an output voltage of the temperature-dependent voltage source to a temperature detecting device having a diode characteristic and for generating a control current having a magnitude in proportion to a current flowing through the temperature detecting device; and a timer period generating circuit for generating a timer period in inverse proportion to the magnitude of the control current.

Self-refresh timer circuit and method of adjusting self-refresh timer period

A delay circuit comprises: N-stage circuits having a first circuit to an N-th circuit connected in cascade, the input signal being input to the first circuit and a transmission signal delayed by a (k-1)-stage (where 2&#x2266;k&#x2266;N) circuit is input to a k-th circuit for sequential transmission; a common delay circuit for delaying the transmission signal of each stage commonly; and path control means for controlling a path of an i-th (1&#x2266;i&#x2266;N) circuit so that during a predetermined period from an edge timing of a signal input to the i-th circuit to an edge timing of the transmission signal delayed by the common delay circuit through the i-th circuit, the common delay circuit is connected to a signal path, and during the other period, the common delay circuit is disconnected from the signal path, wherein the delayed signal passing through the common delay circuit N times is generated.

Delay circuit and semiconductor device

A delay circuit comprises: N-stage circuits having a first circit to a N-th circuit connected in cascade, the input signal being input to the first circuit and a transmission signal delayed by a (k-1)-stage (where 2&#x2266;k&#x2266;N) circuit is input to a k-th circuit for sequential transmission; a common delay circuit for delaying the transmission signal of each stage commonly; and path control means for controlling a path of an i-th (1&#x2266;i&#x2266;N) circuit so that during a predetermined period from an edge timing of a signal input to the i-th circuit to an edge timing of the transmission signal delayed by the common delay circuit through the i-th circuit, the common delay circuit is connected to a signal path, and during the other period, the common delay circuit is disconnected from the signal path, wherein the delayed signal passing through the common delay circuit N times is generated.

A semiconductor memory device is disclosed that is capable of outputting in the fastest possible time the first of serial data that are read in bursts, despite the increase in capacity of a memory cell array. In this semiconductor memory device, for a single address access, a plurality of bits of serial data are read in a burst from a memory sub-array that is made up by memory cell arrays U and U or memory cell arrays L and L In order that the serial data that are read first are the data of bit regardless of the operation mode of the semiconductor memory device, each individual memory sub-array is divided between portions for even data and portions for odd data and the even memory cell arrays U and L in which the data of bit are stored are arranged closer to the data amplifier than the odd memory cell arrays U and L The maximum length of I/O lines that are used in reading even data is therefore about half that of the maximum length of I/O lines that are used in reading odd data.

Semiconductor memory device

In a bandgap reference voltage generating circuit having first, second and third unitary circuits connected in parallel between a power supply voltage and a ground, there is added a fourth unitary circuit including an n-channel FET turned on in response to a bias voltage applied to a gate of the n-channel FET. The second unitary circuit is connected to the fourth unitary circuit through a capacitor having one end connected to a drain of the n-channel FET. When the bias voltage is applied to turn on the n-channel FET of the fourth unitary circuit, since the potential of the one end of the capacitor is dropped, a gate potential of n-channel FETs included in the first and second unitary circuits and operating in a weak inversion condition quickly becomes definite, so that a reference voltage can be generated quickly.

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Tokyo, Japan

Tadashi Onodera