Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Tadashi Ono

Katsuhiko Kumakura

Tatsuro Juri

Isao Kato

Akira Iketani

Takuji Maeda

Masakazu Nishino

Tatsuya Adachi

Chiyoko Matsumi

Masahiro Nakanishi

Shinichiro Nishioka

Susumu Yamaguchi

Hideki Otaka

Shigeru Awamoto

Minoru Kouda

Makoto Goto

Takao Kashiro

Yoshihisa Inagaki

Tomotaka Kawano

Tsutomu Sekibe

Hiroshi Suenaga

Hideyuki Yamada

Hiroyuki Uenaka

Shoji Katori

Masaaki Kobayashi

Masahiro Nakamura

Toshiyuki Honda

Akihiro Miyazaki

Masayuki Toyama

Junji Yoshida

Yuji Fujiwara

Shigenori Maeda

Toshimasa Takaki

Souichirou Fujioka

Satoshi Inami

Masataka Higuchi

Joerg Vogler

Gerald Pfeiffer

Shuichi Ohki

Fukutaro Sekine

Youichi Amano

When a host-slave system including a host device and a slave device transitions to a power-down mode, the host device drives a CMD line in order of a high level, a low level, and a high level, and stops supplying a clock signal after a predetermined time elapses. During a power-down mode period, the slave device stops supplying a power to a back-end module. When the host device resumes the supply of the clock signal, the host-slave system returns from the power-down mode.

Slave device and host device

A data transfer system includes a slave device, and a host device that is connected to the slave device via at least a power supply line, a clock line, a command line, and a data line. A CMD line is continuously driven to a low level in a period from when the supply of at least a first clock is stopped to when the second clock is supplied (period form timing tto timing t).

Host device connected to slave device and data transfer system wherein voltage levels are driven high or low based on a plurality of clock signals

A slave device continuously transmits a plurality of tuning blocks to a host device at intervals defined by a clock period between a plurality of data blocks at the time of transmitting the plurality of data blocks and by a clock period defined by a data structure of the plurality of tuning blocks.

Host device, slave device, and data transfer system

When a part of a signal line of a first interface and a part of a signal line of a second interface share a signal line and there is a memory connected to both the interfaces, initialization of the second interface and initialization of the memory are executed in parallel following initialization of the first interface.

Communication device and communication method

A card device according to an aspect of the present disclosure includes: a first interface that connects the card device with a host device. The card device notifies, through the first interface, the host device of whether or not the card device includes a second interface different from the first interface.

Card device, host device, and communication method

In a removable system formed from a host device and a slave device detachable from the host device, when the slave device sequentially detects a signal of a first voltage level and a signal of a second voltage level from the connected host device, the signal of the first voltage level is transmitted by a second signal line. Subsequently, when the host device detects that the second signal line is at the first voltage level, the host device interrupts drive of a first signal line, and executes initialization.

Host device, slave device, and removable system

Provided is a memory device with improved memory region usage efficiency. The memory device includes flash memory including: a control information (FAT) region that stores FAT for a file and a user data (UD) region that stores UD; cache memory including a FAT cache region that stores all or part of the FAT; an I/F that receives a write command for writing one of the FAT and the UD; and a memory controller that determines whether write data to be written is the FAT or the UD based on an address included in the write command, and sets the size of the FAT cache region based on an update frequency or an update count for the address included in the write command for the write data determined to be the FAT by the determiner.

Memory device and method for controlling memory device

An access deviceincludes an access speed information partfor informing an access speed required for data recording by the access deviceto a nonvolatile memory deviceThe nonvolatile memory device includes an access condition determination partfor determining an access condition required for meeting the informed access speed and an access area determination unitfor determining an access area according to the determined access condition. The access deviceinforms the required access speed to the nonvolatile memory devicein advance so that the access condition determination partand the access area determination partin the nonvolatile memory devicerealize data recording which meets the access speed informed in advance upon the data recording. Thus, it is possible to access all the nonvolatile memory devices at a desired speed regardless of difference in characteristics of the recording speed of each of the nonvolatile memory devices.

Nonvolatile memory device, access device, and nonvolatile memory system

In a communication system in which data is transmitted and received in synchronization with a clock signal, a peripheral device cannot transfer data to a host device when the host device stops outputting the clock signal and thus the peripheral device cannot promptly transmit an interrupt request to the host device. A peripheral device transmits an interrupt request to a host device using a signal line for a clock signal when the clock signal output has been stopped. The host device receives the interrupt request, and resumes outputting a clock signal to enable data transmission and reception to and from the peripheral device. This enables the peripheral device to transmit an interrupt request to the host device promptly when the output of the clock signal from the host device has been stopped.

Enabling a peripheral device to transmit a request for interrupt processing to a host when no clock signal is output from the host device

A host device and a slave device are set to a full-duplex mode by temporarily switching the communication direction of a first transmission channel or a second transmission channel after completing transmission and reception of a predetermined number of data packets in the half-duplex mode. The host device or the slave device can thus transmit an interrupt request, such as a request associated with a wait status or a busy status, to its communication target using the temporary full-duplex mode. This enables the host device or the slave device to process such an interrupt request during high-speed data transfer performed in the half-duplex mode.

Interface device, communications system, non-volatile storage device, communication mode switching method and integrated circuit

In a memory system including a host device and one or more nonvolatile memory devices, the host device reads, from a nonvolatile memory device connected in the system, a boot code used to operate a CPU of the host device before the CPU is activated. The boot code reading process is required to be performed with a simple method. A host device () transmits a first symbol including a synchronous code to a nonvolatile memory device (). The nonvolatile memory device () receives the first symbol from the host device (), and transmits a first symbol that is identical to the received first symbol to the host device (), and then transmits a boot code to the host device (). In this manner, the host device () reads a boot code from the nonvolatile memory devicewith a simple method.

Non-volatile storage device, host device, storage system, data communication method and program

Without corresponding to different address spaces between an access device and a nonvolatile memory device, the access device designates a file ID to manage a data storing state only in a physical address space in the nonvolatile memory device. The access device sends the nonvolatile memory device a transfer rate through a transfer rate transmitting unit. A filling-up rate calculating unit calculates a filling-up rate of a physical block corresponding to an assurance speed required by the access device. A remaining amount corresponding to the transfer rate is sought by using the calculated filling-up rate and is transmitted to a remaining amount receiving unit of the access device.

Memory controller, nonvolatile memory device, access device, and nonvolatile memory system

A data communication system for starting transmission and reception of target data for processing upon recognition that switching between communication modes is completed. The data communication system includes a master communication device and a slave communication device that continuously perform, at a time of switching from half-duplex communication to full-duplex communication, (i) a handshake using a directional control code indicating the switching and a preamble code indicating completion of the switching and (ii) a handshake using the preamble code and an acknowledge code indicating receipt of the preamble code, whereby each of the devices recognizes that the switching between communication modes by the opposite device is completed and starts transmission and reception of the target data.

Data communication system, communication device, and communication method

The access devicedesignates a file ID without relating different address spaces of an access deviceand a nonvolatile memory devicewith each other and manages a data storing state only in a physical address space in the nonvolatile memory device. The access devicesends a transfer rate to the nonvolatile memory deviceby using a transfer rate sending part. A filling rate calculation partcalculates a filling rate of physical block corresponding to a guaranteed speed required by the access device. A remaining capacity corresponding to the transfer rate is obtained by using the calculated filling rate and is sent to a remaining capacity receiving partof the access device

In a normal operation state, a connection management section writes data transmitted from a first processing section to a data temporary storage section and reads data to be received by a second processing section from the data temporary storage section. Upon receiving control signals which instruct a change of the subject of processing, the first processing section and the second processing section output a transmitting-end clear request and a receiving-end clear request, respectively. The connection management section reads data from the empty data storage section after a transmitting-end clear request is received and until a receiving-end clear request is received, and writes data to the empty data storage section after a receiving-end clear request is received and until a transmitting-end clear request is received.

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Osaka, Japan

Tadashi Ono