Kabushiki Kaisha Toshiba

Kabush″ei Kaishr Toshiba

Tadashi Onizawa

Masaru Koyanagi

Yutaka Tanaka

Natsuki Kushiyama

Shigeyuki Hayakawa

Katsuki Matsudera

Tsuyoshi Midorikawa

A semiconductor integrated circuit device includes normal bit cells, structural dummy bit cells and timing dummy bit cells having the same structure as that of the normal bit cells, normal word lines electrically connected to the normal bit cells, a first dummy word line electrically coupled to the structural dummy bit cells, and a second dummy word line electrically coupled to the timing dummy bit cells. The second dummy word line is connected in parallel with the first dummy word line.

Semiconductor integrated circuit device

A semiconductor integrated circuit includes first and second MOS transistors and a capacitor. The first MOS transistor has a drain connected to an output terminal, a gate and a source. The second MOS transistor has a gate, a drain connected to the source of the first MOS transistor and a source and has the same conductivity type as the first MOS transistor. The capacitor has one electrode connected to the gate of the first MOS transistor and the other electrode connected to a node whose potential changes in a complementary fashion with respect to the drain potential of the first MOS transistor and functions to cancel out an influence, caused by the coupling of a mirror capacitor which exists between the gate and drain of the first MOS transistor, affecting the gate potential of the first MOS transistor.

Semiconductor integrated circuit having output buffer

Growing community of inventors

Yokohama, Japan

Tadashi Onizawa