Hitachi, Ltd.

Hitachi Information Control Systems, Inc.

Tadashi Okamoto

Hiromasa Yamaoka

Noboru Azusawa

Kazuhiko Shimoyama

Takeshi Katoh

Makoto Tachikawa

Junichi Hamano

Akihiro Ohhashi

Hitoshi Saitoh

Kouichi Kimura

Yuzaburo Iwasa

Mitsuro Takakura

A process controlling method and apparatus which uses a flowchart language program and ladder programs with an intermediate register accessible using the same name by both the flowchart language program and the ladder programs. Each ladder program defines the operation of a machine, including an interlock condition of the machine operation. The flowchart language program defines an automatic operation flow which sequentially activates the ladder programs using the data in the intermediate register. This arrangement allows the flowchart language program to be separated from the ladder programs improving productivity, serviceability and security of the programs.

Apparatus and method for controlling a system process

A microprogram load unit comprising a readable and writable microprogram memory within a central processor unit for storing microprogram, a relatively low speed, readable and writable, nonvolatile memory unit, and a readable and writable memory with battery backup. It is determined whether data of the readable and writable memory with backup has been lost or not when power is turned on. If data loss is not present, microprogram is read out of the readable and writable memory with backup and written into the microprogram memory. If data loss is present, microprogram is read out of the nonvolatile memory unit and is written into the microprogram memory.

Microprogram load unit

A process controlling method uses a flowchart language program and ladder programs with an intermediate register to be accessible with the same name by both the flowchart language program and the ladder programs. Each ladder program defines the operation of a machine, including an interlock condition or the like of the machine operation. The flowchart language program defines an automatic operation flow which sequentially activates the ladder programs using the data in the intermediate register. This arrangement allows the flowchart language program to be separated from the ladder programs, thereby improving productivity, serviceability and security of the programs.

Microprogram load unit having alternative backup memory sources

A multiplex control system has controllers for delivering control data to at least one common controlled system, and a multiplex mode switching device which is constructed to permit the logic for selecting the control data to be changeably set therein. The mode selection logic of the multiplex mode switching device can be set and changed freely by the user so that a desired logic is obtainable for the selection of the control data from the controllers, whereby the adaptability and utility of the multiplex control system are increased.

Multiplex control system with programmable logic for controlling signal

A programmable controller for controlling a plant on the basis of a stored program includes a processing unit for reading out an instruction from a program memory to process the instruction. In the processing unit, it is determined whether the instruction read out from the memory is an instruction taking a register-modified addressing mode or an instruction taking a direct addressing mode. When the read-out instruction is an instruction taking the direct addressing mode, a plant is directly addressed by the address part of the instruction. Then, an arithmetic operation is performed using the state information which is read out from the plant thus addressed, or plant control information is sent from the processing unit to the plant thus addressed.

Programmable controller with direct to plant addressing

A relay ladder sequence circuitry having i columns and j rows is divided into a plurality of sections each having a predetermined number of rows, and the bit informations are processed in a parallel manner in the rows of the sections. More specifically, the program in accordance with the sequence ladder construction is memorized and are successively read out as the addresses of the program are appointed. The signals of relay contacts as the bit information are processed for each line in accordance with the read out program, so that a high processing speed is attained.

Bit processing utilizing a row and column ladder sequence

A digital controller for controlling a plurality of processes. In view of the fact that in case a plurality of processes of a like nature are to be controlled, same operands are used for performing a similar arithmetic operation a number of times, instructions are stored in a common memory for simplifying the programming, while the operands are stored in memories each incorporated in each of the processors adapted for controlling individually the objective processes, to thereby allow arithmetic processings to be performed by the processors in parallel with one another. Overall processing speed is made thus significantly high.

Growing community of inventors

Hitachi, Japan

Tadashi Okamoto