Matsushita Electric Industrial Co., Ltd.

Matsushita Electrical Industrial Co., Ltd.

Matsushita Electric Industrial

Matsushita Electrical Co. Ltd.

Tadashi Okamoto

Hiroshi Kadota

Yoshiteru Mino

Shinji Sasaki

Ichiro Okabayashi

Shinji Furuya

Satoshi Shigenaga

Masaitsu Nakajima

Jiro Miyake

Koji Zaiki

Tomohiro Okada

Yoshinori Maeda

To provide an apparatus for painting figures which is improved in painting capability better than the conventional art even when a path to an external memory section is narrow. In order to simultaneously write previously generated painting information and read data required for generating painting information later in the painting coordinate generating section and the painting information generating section on the painting apparatus, while painting information is generated, first and second buffers are provided as a buffer section for storing painting information generated in the painting information generating section, and address information storing sections corresponding to the first and second buffers are provided as an address generating section for generating an address for storing painting information, which is accumulated in the buffer section, in an external memory section. When reading and writing is carried out on the first buffer, the following operations are performed in parallel: outputting data, which is previously written to the second buffer, to the external memory section, reading data required for the next processing from the external memory section.

Apparatus for painting figure

A polygon drawing apparatus for drawing a polygon which is colored inside its outline by using outline data indicating the outline of the polygon, the apparatus comprising: an outline data generation unit for generating outline data indicating the outline of the polygon on the basis of coordinate data indicating the coordinates of points constituting the polygon; a mask data generation unit for performing, for a predetermined amount of the outline data, parallel exclusive-OR processes in units of amounts constituting the predetermined amount, thereby generating mask data which specifies &ldquo;coloring&rdquo; for the inside of the outline; and a segment generation unit for drawing the polygon by using the mask data generated by the mask data generation means. Therefore, this polygon drawing apparatus can provide a satisfactory result of display without using a bulk memory, and without increasing the processing load.

Polygon drawing method and polygon drawing apparatus

A bus for data transmission, bus switches for slicing the bus, and four arithmetic blocks are provided to perform a series of fixed-point arithmetic operations. Each of the four arithmetic blocks has a plurality of digit-serial arithmetic units, namely a multiplier, an adder/subtracter, and a shifter. Each of the digit-serial arithmetic units has the functions of receiving a plurality of input digits representative of an input operand and a digit position indicator of each of the input digits and providing a plurality of result digits representative of an arithmetic result of the input operand and a digit position indicator of each of the result digits to any other one of the plurality of digit-serial arithmetic units. Particularly, the digit-serial adder/subtracter contains therein a selector for input switching so that the digit-serial adder/subtracter can perform butterfly arithmetic.

Reconfigurable digit-serial arithmetic system having a plurality of digit-serial arithmetic units

Five processing units, namely one data memory, three arithmetic units, and one data memory, are connected together in a cascade arrangement so as to form a single arithmetic pipeline. Likewise, five control devices are connected together in a cascade arrangement and a control signal requesting that a series of data processing operations should start is sent to the first stage control device. Each control device starts to send a micro instruction to a corresponding processing unit upon detection of a processing start request bit in the received control signal and sends a signal which lags the control signal by a delay time equal to a number of cycles required to complete a processing operation of the processing unit, to the next stage control device. The first stage control device is provided with a loop counter operable to count the number of times processing is repeated and automatically generates a processing start request and a processing end request to the next stage control device.

Cascaded arithmetic pipeline data processor

A data processor of the invention includes plural memories, plural arithmetic units, a data transfer unit and a network. The data transfer unit transfers various data to predetermined memories, and switches the connections between the memories and the arithmetic units by using the network. The control unit adds a processability judgement signal to a data read from a predetermined memory in reading the data, so as to make a pair of the data and the processability judgement signal. Each of the arithmetic units receives the data and the processability judgement signal, conducts predetermined processing on the received data, delays the received processability judgement signal by the number of cycles equal to its own processing cycle, and outputs resultant data obtained through the processing and the delayed processability judgement signal. Accordingly, in storing ultimate resultant data in a predetermined storage unit, the storage unit stores the ultimate resultant data as effective data on the basis of the processability judgement signal added to the resultant data. The data processor attains wide application and can be applied to various types of multimedia applications by switching the connections between the memories and the arithmetic units by using the network.

Data processor

A data readout time adjuster to be used for a video-on-demand system includes the following units. A readout time adjusting data storage unit stores image data for adjusting readout time to be provided to subscribers who have not been assigned the readout right and are waiting for a start of a readout operation. The image data for adjusting readout time cause no inconvenience even if a transmission of the image data is interrupted any time. A readout start position check unit checks an expected time of an occurrence of the readout right and a readout start position at the expected time in response to an additional data transmission request. A readout control unit makes at least one of the readout unit and a private readout unit exclusively provided or the readout time adjusting data storage unit read the image data for adjusting readout time stored in the readout time adjusting data storage unit until the time of the occurrence of the readout right, for the subscribers who have checked the expected time and the readout start position. A readout time adjusting data transmission control unit controls the transmission unit to transmit the image data for adjusting readout time read by the readout control unit to the subscribers who are waiting for the readout right until the time of the occurrence of the readout right.

Image data readout time adjuster for a video-on-demand system

A video-on-demand system divides compressed image data of a video program into image data sections with a predetermined length and stores them in one of a series of storage media in order of reproduction, returning to a first storage medium in the series after reaching a final storage medium in the series, along a story of the video program. The image data sections stored in the storage media are read by time sharing and the original images are reproduced and displayed.

Video-on-demand system uses adjusting positions of slots in a slot table

An image processing apparatus which performs a process which enhances incongruous pixel values in an original image, including an object pixel selecting unit for selecting an object pixel out of pixels which compose the original image, a plurality n of filter units, each of which extracts pixel values of a set of pixels, including the selected object pixel, on one of a predetermined surface and a predetermined line which pass through the object pixel, out of pixels in a predetermined range, wherein each predetermined surface and predetermined line is at a different inclination, a relative size comparing unit for comparing pixels values of each set of pixels extracted by each filter unit and specifying a filter unit whose pixel values best approximate to a predetermined standard, and a first pixel value enhancing unit for enhancing a pixel value of the object pixel based on only the pixel values of the specified filter unit.

Image processing apparatus and image processing method for favorably

The present invention is a video-on-demand system, comprising an image data storage device, including a plurality of recording media, which stores image data for a plurality of programs divided into a plurality of blocks which are distributed among all of the recording media, an image data management device, including image data management tables in which management information for the image data is stored, which consults the image data management tables and transmits necessary information separately for each block, when there is a request from outside the device for information about one of the programs, these image data management tables including a title table corresponding a title of each of the programs with starting block identification information for each, a block table corresponding block identification information for each of the blocks with starting frame identification information for each block, and a frame table corresponding frame identification information for each frame with position information showing at which position on which recording medium out of the recording media each of the frames is stored, and an image data transmission device which requests to the image data management device for the necessary information for a transmission of a program requested by a user, receives the necessary information from the image data management device, retrieves image block data separately for each block from the recording media and transmits the image block data to the user.

Video-on-demand system of reduced storage capacity which can provide

A processor having a memory for use as a stack and a stackpointer provided within the processor, includes circuits for judging a underflow and a overflow of the memory by receiving address of the stackpointer and a signal showing a stack operating instruction from an instruction decoding part in the processor, so as to be capable of calling a subroutine at a high speed, and judging and preventing an overflow or underflow of the stack.

Processor having a stackpointer address provided in accordance with

An address conversion apparatus includes a content addressable memory for storing a plurality of logical addresses, and a random access memory for storing a plurality of physical addresses corresponding to the logical addresses. When an input logical address is received, a search is conducted to find the same logical address stored in the memory. When the same logical address is found, the content addressable memory causes the random access memory to output a corresponding physical address. The content addressable memory includes a plurality of logical address storage units. Each unit has a plurality of data bit cells for storing address data and a process identification number cell for storing a process identification number. Thereby, a plurality of logical addresses which correspond to different processes are stored in the single content addressable memory.

Address conversion apparatus

A memory device includes plural word data storing rows. Each word data storing row is composed of a plurality of data bit cells for storing the word data, and a valid bit cell for indicating the validity of data. The valid bit cell has a reset circuit composed of FETs, and the reset circuits are connected to one reset line. By applying a reset signal to one reset line, plural valid bit cells are reset as a batch.

Growing community of inventors

Osaka, Japan

Tadashi Okamoto