Kabushiki Kaisha Toshiba

Tadashi Matsuno

Hideki Shibata

Masahiro Inohara

Noriaki Matsunaga

Minakshisundaran Balasubramanian Anand

Katsuya Okumura

Hisashi Kaneko

Kazuyuki Higashi

Akihiro Kajita

Naofumi Nakamura

Tetsuo Matsuda

Tadashi Iijima

Takamasa Usui

Hideshi Miyajima

Hisayo S Momose

Kazuhiko Hashimoto

Tamao Takase

A semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconductor substrate, and forming a lower level wiring in the trench, a step of forming at least one conductive layer on the semiconductor substrate to coat the lower level wiring, a step of forming at least one thin film layer on the conductive layer, a step of forming a hard mask by patterning the thin film, a step of etching the conductive layer by using the hard mask as an etching mask, and forming a conductive pillar-shaped structure, whose upper surface is covered with the hard mask, on the lower level wiring, a step of forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, a step of forming a wiring trench in which at least the hard mask is exposed, and a step of burying a conductor into the wiring trench after the hard mask is removed, and forming an upper level wiring in the wiring trench.

Semiconductor device manufacturing method and semiconductor device

A semiconductor apparatus and a process for fabricating the same according to the invention permit reduction in width of a wiring pattern of the semiconductor apparatus and in distance between wiring elements. A stopper film and an insulating film are provided on a substrate. The etching rate of RIE for the insulating film is greater than that for the stopper film. The stopper film and insulating film are formed on the insulating film. A pattern of the contact hole is formed in the stopper film. A wiring pattern is formed on the resist film. The insulating films are etched by RIE with the resist film and stopper film used as masks. Thus, a groove for formation of wiring and a contact hole for formation of a contact plug are simultaneously formed in a self-alignment manner.

Semiconductor apparatus having wiring groove and contact hole in

This invention is related to a metallization of Cu. The semiconductor device comprises a first insulating layer having a groove in a surface thereof, a second insulating layer on a surface of the groove, made of a material having a low density of crystal defects in comparison with that of the first insulating layer, and a wiring layer buried in the groove, surrounded by the second insulating layer.

Semiconductor device and method of manufacturing the same

The present invention intends to form multilayer interconnects without deteriorating the advantage of an organosiloxane film (an interlayer dielectric), i.e., the low dielectric constant. According to the present invention, an organosiloxane film, a silicon nitride film, an inorganic SOG film, and a photoresist pattern are formed on a first metal layer, in series. The inorganic SOG film is then etched with use of the photoresist pattern as a mask to transfer the photoresist pattern to the inorganic SOG film. The photoresist pattern is then removed by oxygen plasma treatment with use of the silicon nitride film as a protection mask for protecting the organosiloxane film. Subsequently thereto, the silicon nitride film and the organosiloxane film are etched with use of the inorganic SOG film to form a contact hole reaching the first metal layer. After removing the inorganic SOG film, a second metal layer is formed to contact with the first metal layer through the contact hole.

Manufacturing method of semiconductor device

A semiconductor device includes a substrate, an insulation film formed above the substrate and containing silicon-fluorine bonds, and a titanium-based metal wiring layer formed on the insulation film, the titanium-based metal wiring layer containing fluorine which is diffused from the insulation film and has a fluorine concentration of less than 1.times.10.sup.20 atoms/cm.sup.3.

Semiconductor device with improved adhesion between titanium-based metal

Method of making semiconductor apparatus having wiring groove and

In a method of manufacturing a semiconductor device, when a copper diffusion preventing film portion on the connecting hole bottom portion is to be removed, a film thickness of other portion of the copper diffusion preventing film not to be removed is more thickly formed than that of the to-be-removed copper diffusion preventing film portion on the connecting hole bottom portion, thereby only the copper diffusion preventing film portion to be removed can be removed. The method can extend a durable length of time of a wire and can reduce a resistance of the metal wires in a connecting hole bottom portion by removing a copper diffusion preventing film on the bottom portion of the connecting hole.

Method of manufacturing semiconductor device having multi-layer wiring

A method for fabricating a semiconductor device at low cost is provided in which a mask layer having a very large polishing selection ratio is used as a polishing stop film by forming the polishing stop film in self-alignment. An object layer to be flattened is formed on a substrate. The object layer contains an irregularity. A polishing stop film which is polished at a slower rate and a mask layer which is polished at about the same rate as the object layer are deposited on the object layer. Then, the mask layer on a high level portion of the object layer is removed by chemical-mechanical polishing. The polishing stop film is etched other than under the mask layer, so that the polishing stop film at the high level portion and side wall of the step is removed. Because the polishing stop film at the convex portions (high level portion) is removed by etching utilizing a chemical reaction without using chemical-mechanical polishing, it is possible to select a material for the polishing stop film which is polished at a very slow rate. After that, the mask layer and the object layer at the convex portion are removed by CMP to level off the object layer with the concave portion.

Manufacturing method of semiconductor device using chemical mechanical

Semiconductor device having a second insulating layer which includes

The present invention provides a semiconductor device including an improved buried electrode formed by selective CVD. In this semiconductor device, a first insulation layer is formed on a semiconductor substrate. A first conductive layer is formed along an inner surface of a recess of an opening formed on the first insulation layer. A second conductive layer is formed on the first conductive layer in the recess of the opening. The second conductive layer is flush with the first insulation layer. The surfaces of the first and second conductive layers are coated with a third conductive layer. A second insulation layer is formed on the first insulation layer and the third conductive layer. A via hole is formed through the second insulation layer and the third conductive layer and reaches to the second conductive layer. A buried electrode layer is grown in the via hole and formed in contact with the second conductive layer. A fourth insulation layer has a group of conductive layers formed on the second insulation layer and the buried electrode layer and electrically connected to the second conductive layer through the buried electrode layer formed in the via hole.

Method of forming semiconductor device having an improved buried

A method of manufacturing a semiconductor device having a semiconductor substrate of a first conductivity type, an N-type diffusion layer formed in the substrate, and a P-type diffusion layer formed in the substrate. Two contact holes are formed in separate steps, thus exposing the N-type diffusion layer and the P-type diffusion layer, respectively. Hence, when one of the diffusion layers is again doped with an impurity, or again heat-treated, the other diffusion layer is already protected by inter-layer insulation film. Therefore, the impurity cannot diffuse into the contact formed in the contact hole made in the other diffusion layer. As a result of this, SAC technique can be successfully achieved, without deteriorating the characteristic of the contact. In addition, since two contact holes are made in a polysilicon wiring strip and the diffusion layer to which the SAC technique is applied, in separate steps, the SAC technique can be successfully accomplished, without deteriorating the characteristic of the MOSFET formed in the semiconductor device.

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Yokohama, Japan

Tadashi Matsuno