Kabushiki Kaisha Toshiba

Fujitsu Corporation

Mitsubishi Rayon Company, Limited

Mitsubishi Rayon Engineering Co., Ltd.

Fumitsu Limited

Tadashi Matsuda

Tsuneo Mizuno

Fumitaka Abe

Tomohisa Mikami

Noboru Takada

Masatoshi Kimura

Tetsujiro Tsunoda

Masakazu Yamaguchi

Masahiro Tanaka

Hideaki Habara

Junzo Nakajima

Tohru Satoh

Michio Shimura

Shinichi Umekawa

Munehiro Okumura

Shuichi Sugimori

Tomihiko Kawamura

Shigeru Yoshikawa

Shinichi Ishii

Fumio Sakurai

Hideki Hattori

Shojiro Kido

Takao Nomura

Shintaro Nakano, Deceased

Sumito Saiki

According to one embodiment, an information processing apparatus includes a memory unit which stores attribute information which indicates a characteristic quantity of each of components constituting a product, and parent-child relationship information which indicates a parent-child relationship between the components, a unit which calculates positions on a tree diagram of nodes corresponding to the components, a unit which calculates, for each of the components, a sum of the characteristic quantity of the component and the characteristic quantities of all child components belonging to the component, a unit which determines, for each of the nodes, a mode of a branch line which is to connect the node to a parent node thereof, based on the sum calculated for each of the components, and a unit which creates the tree diagram based on the calculated positions of the nodes and the determined mode of the branch line corresponding to each node.

Information processing apparatus and program for displaying tree diagram

A semiconductor device includes a trench gate IGBT and a MISFET. The IGBT has an auxiliary base layer which is formed in an arbitrary region between two adjacent trenches and is insulated from an emitter electrode of the IGBT, and a carrier discharge electrode which contacts a surface of the auxiliary base layer. The MISFET is connected to the emitter electrode and the carrier discharge electrode and turned on upon turning off the IGBT. Upon turning off the IGBT, the accumulated carriers below the auxiliary base layer are discharged to the emitter electrode via the auxiliary base layer, the carrier discharge electrode, and the MISFET. This promotes the carrier discharge effect in turn-off, realizing a high-speed turn-off characteristic.

Semiconductor device

The power semiconductor device includes a plurality of trenches disposed in a surface of a semiconductor active layer to reach a first base layer of a first conductivity type. The trenches are disposed at intervals to partition a main cell and a dummy cell. In the main cell, a second base layer of a second conductivity type and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode and gate insulating film are disposed in each trench. A partition structure is disposed in the surface of the semiconductor active layer to electrically isolate the buffer layer from the emitter electrode.

Power semiconductor device

An insulated gate bipolar transistor includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type formed on a top surface of the first semiconductor layer, a base layer of the first conductivity type formed on a top surface of the second semiconductor layer, a plurality of gate electrodes each of which is buried in a trench with a gate insulation film interposed therebetween, the trench being formed in the base layer to a depth reaching said second semiconductor layer from a surface of the base layer, each the gate electrode having an upper surface of a rectangular pattern with different widths in two orthogonal directions, the gate electrodes being disposed in a direction along a short side of the rectangular pattern, and emitter layers of the second conductivity type formed in the surface of the base layer to oppose both end portions of each the gate electrode in a direction along a long side of the rectangular pattern.

Insulated gate bipolar transistor having trench gates of rectangular upper surfaces with different widths

A semiconductor device in accordance with present invention includes a first conduction type first semiconductor layer; a second conduction type second semiconductor layer which is formed on the first semiconductor layer and has a substantially uniform impurity concentration; a plurality of first conduction type base layers formed in the surface of the second semiconductor layer; a plurality of second conduction type emitter layers formed in the surfaces of the respective base layers; channel regions formed in the surfaces of the respective base layers and between the emitter layers and the second semiconductor layer; a first conduction type auxiliary base layer formed in the surface of the second semiconductor layer between two base layers adjacent to each other; a gate electrode formed via a gate insulating film on the second semiconductor layer between the auxiliary base layer and the two base layers and on the channel regions; an emitter electrode connected to the base layers and the emitter layers; and a collector electrode connected to the first semiconductor layer.

Insulated gate bipolar transistor

An Insulated Gate Bipolar Transistor (IGBT) having a new structure capable of performing a low on-voltage and a high-speed turn-off is provided. A P-type collector region 1 of IGBT is not formed on the entire reverse surface of an N-type base region 2, but formed only on its part, and a metal collector electrode 9 is electrically connected only with the surface to which the P-type collector region 1 exposes. An area of a diffusion window in a collector region is relatively reduced, whereby the impurity concentration of the entire collector region is set at a lower value and hole injection efficiency is decreased. At the same time it is possible to obtain high surface concentration with deep diffusion depth of the collector region required to form a favorable ohmic contact.

High switching speed IGBT

A conductivity modulation type field effect transistor comprises an n.sup.- type low concentration impurity layer of high resistance formed on an n.sup.+ type silicon substrate, a first channel region of a given width formed on the low concentration impurity layer, a pair of p type gates oppositely formed with the first channel region therebetween, an n.sup.- type low concentration impurity layer formed on the first channel region including the p.sup.+ gate, a p channel layer including two channel regions formed on the n.sup.- type low concentration impurity layer, and a pair of n.sup.+ type sources formed on the second channel region with their center aligned with a center of the first gate means, in which, after the formation of the n.sup.+ type source, a groove is formed at each side of a respective semiconductor device, first gate electrodes are provided on the bottom surface and side wall of the groove with a gate oxide film therebetween whereby the transistor has the blocking capability of achieving a normally OFF state.

Conductivity modulation type insulated gate field effect transistor

A semiconductor device for accomplishing high speed switchings with a large current includes a radiation plate, a first conductor fixed on said radiation plate, a first insulating layer fixed on said first conductor, a second conductor fixed on said first insulating layer, at least one semiconductor element and a second insulating layer fixed on said second conductor, a third conductor fixed on said second insulating layer, a fourth conductor for electrically connecting the surface electrode of said semiconductor element with said third conductor, a first power terminal fixed on said second conductor, and a second power terminal fixed on said third conductor. To reduce the internal inductance, said first and second power terminals have a flat part whose width is larger in length than the height. Also, these terminals are adjacently arranged substantially parallel to each other. In this device, the main currents on said first and second power terminals, and on said second and fourth conductors flow in the opposite directions, thus further reducing the internal inductance.

Semiconductor device having a particular terminal arrangement

A porous water-treating material comprising cut porous strands each comprising a resinous matrix material which consists essentially of a thermoplastic polymer material or a mixture thereof with an inorganic particulate material. Each strand having a number of pores connected to each other and an irregularly rugged peripheral surface which has a ratio in diameter of a circumscribed circle to an inscribed circle in any cross-sectional profile from 1.10:1 to 5.00:1 and a ratio of the distance between circumscribed lines to that between inscribed lines in any side projection profile of from 1.10:1 to 3.00:1. The cut porous strands are prepared by melt-extruding a resinous mixture of the resinous matrix material with a blowing agent at a temperature higher than the melting point of the thermoplastic polymer material and the thermally decomposing point of the blowing material so as to cause the strands to have a number of pores and an irregularly rugged peripheral surface thereof.

Process of using a porous water-treating material

This invention provides an aerator comprising a jet stream generator for ejecting a gas and a liquid in a mixed state from a nozzle, and a tubular flow straightener for mixing the bubble-containing stream ejected from the nozzle with ambient water and discharging the resulting mixture from the discharge orifice thereof, characterized in that the flow straightener has a tubular form whose internal diameter is reduced from the inlet toward the discharge orifice through at least a part of its length. This aerator can produce a stream containing minute gas bubbles, even when a gas is supplied thereto in such a large amount as to give a gas-to-liquid volume ratio of 3/1.

Aerator and aerobic biological treatment process using same

An apparatus for ejecting droplets of ink including: a passage for ink; an orifice disposed at one end of the passage; a pressure-applying device for applying a pressure wave to the ink within the passage; and a signal-supplying device for supplying an actuating signal to the pressure-applying device. The frequency of the signal is such that the displacement of the ink surface at the orifice due to the pressure wave is maximized.

Apparatus for ejecting droplets of ink

Ink jet printing head

A method for driving an ink jet printer which includes an electro-mechanical transducer which is operated by electrical pulses to eject ink from an ink nozzle connected to pressure chamber wherein two successive electrical pulses are supplied to the transducer before the ejected ink is separated from the remaining ink in the pressure chamber.

Method and circuit for driving an ink jet printer

A timing pulse generator for producing timing pulses the period of which is variable. In the timing pulse generator, a plurality of reference pulse trains are produced which have the same frequency as each other, but different phases from each other. Then, each of the pulses comprising the final timing pulses to be produced is created by suitably selecting one of the pulses from among the reference pulse trains, sequentially.

Growing community of inventors

Yokohama, Japan

Tadashi Matsuda