Ngr Limited

Nanogeometry Research Inc.

Seiko Instruments Inc

Hitachi Metals, Ltd.

Tadashi Kitamura

Toshiaki Hasebe

Masahiro Yamamoto

Kazufumi Kubota

Shinichi Nakazawa

Neeti Vohra

Akio Ishikawa

Masotoshi Tsuneoka

Kenichi Inoue

Koji Utsumi

Shigeyoshi Fujihara

Shinji Kayama

Masatoshi Tsuneoka

A machining condition estimating apparatus, and method, for estimating a machining condition to suppress a wear volume of a tool when conducting cutting work in a work machine are provided. For example, an analysis model presenting shapes of a tool and cutting material, may be defined, to be a target of analysis, and an initial value for use of analysis and change volume of the machining condition parameter as analysis parameters may be set up. Coordinates for tool and cutting material contact may be calculated. Moreover, a boundary movement rate, a maximum contact length, and a contact angle are calculated. A machining condition presented by the analysis parameter may also be searched and outputted.

Machining condition estimating apparatus and machining condition estimating method

A pattern inspection apparatus is used for inspecting a fine pattern, such as a semiconductor integrated circuit (LSI), a liquid crystal panel, and a photomask (reticle) for the semiconductor or the liquid crystal panel, which are fabricated based on data for fabricating the fine pattern such as design data. The pattern inspection apparatus includes a reference pattern generation device configured to generate a reference pattern represented by one or more lines, comprising one of a line segment and a curve, from the data, an image generation device configured to generate the image of the pattern to-be-inspected, a detecting device configured to detect an edge of the image of the pattern to-be-inspected, and an inspection device configured to inspect the pattern to-be-inspected by comparing the edge of the image of the pattern to-be-inspected with the one or more lines of the reference pattern.

Pattern inspection apparatus and method

Apparatus and method evaluate a wafer fabrication process for forming patterns on a wafer based upon design data. Within a recipe database, two or more inspection regions are defined on the wafer for analysis. Patterns within each of the inspection regions are automatically selected based upon tendency for measurement variation resulting from variation in the fabrication process. For each inspection region, at least one image of patterns within the inspection region is captured, a reference pattern, represented by one or both of (a) one or more line segments and (b) one or more curves, is automatically generated from the design data. An inspection unit detects edges within each of the images and registers the image with the reference pattern. One or more measurements are determined from the edges for each of the selected patterns and are processed within a statistical analyzer to form statistical information associated with the fabrication process.

Defect and critical dimension analysis systems and methods for a semiconductor lithographic process

A system and method is described for evaluating a wafer fabrication process for forming patterns on a wafer based upon data. Multiple inspection regions are defined on the wafer for analysis. For each inspection region, images of patterns within the inspection region are captured, edges are detected, and lines are registered to lines of a reference pattern automatically generated from the design data. Line widths are determined from the edges. Measured line widths are analyzed to provide statistics and feedback information regarding the fabrication process. In particular embodiments defects are identified as where measured line widths lie outside boundaries determined from the statistics. In particular embodiments, lines of different drawn width and/or orientation are grouped and analyzed separately. Measured line widths may also be grouped for analysis according to geometry such as shape or proximity to other shapes in the inspection region to provide feedback for optical proximity correction rules.

System and method for a semiconductor lithographic process control using statistical information in defect identification

A fine pattern, such as a semiconductor integrated circuit (LSI), a liquid crystal panel, and a photomask (reticle) for the semiconductor or the liquid crystal panel, which are fabricated based on data for fabricating the fine pattern such as design data is inspected by a pattern inspection apparatus. The pattern inspection apparatus for inspecting a pattern to-be-inspected uses an image of the pattern to-be-inspected and data for fabricating the pattern to-be-inspected. The pattern inspection apparatus includes a reference pattern generation device configured to generate a reference pattern represented by one or more lines from the data, an image generation device configured to generate the image of the pattern to-be-inspected, a detecting device configured to detect an edge of the image of the pattern to-be-inspected, and an inspection device configured to inspect the pattern to-be-inspected by comparing edges of the image of the pattern to-be-inspected with the one or more lines of the reference pattern.

A pattern inspection apparatus is used for inspecting a pattern, such as semiconductor integrated circuit (LSI), liquid crystal panel, and a photomask by using an image of the pattern to-be-inspected and design data for fabricating the pattern to-be-inspected. The pattern inspection apparatus includes a reference pattern generation device for generating a reference pattern represented by one or more lines from design data, an image generation device for generating the image of the pattern to-be-inspected, a detecting device for detecting an edge of the image of the pattern to-be-inspected, and an inspection device for inspecting the pattern to-be-inspected by comparing the edge of the image of the pattern to-be-inspected with the one or more lines of the reference pattern.

A fine pattern, such as a semiconductor integrated circuit (LSI), a liquid crystal panel, and a photomask (reticle) for the semiconductor or the liquid crystal panel, which are fabricated based on data for fabricating the fine pattern such as design data is inspected by a pattern inspection apparatus. The pattern inspection apparatus for inspecting a pattern to-be-inspected uses an image of the pattern to-be-inspected and data for fabricating the pattern to-be-inspected. The pattern inspection apparatus includes a reference pattern generation device configured to generate a reference pattern represented by one or more lines from the data, an image generation device configured to generate the image of the pattern to-be-inspected, a detecting device configured to detect an edge of the image of the pattern to-be-inspected, and an inspection device configured to inspect the pattern to-be-inspected by comparing the edge of the image of the pattern to-be-inspected with the one or more lines of the reference pattern.

First, a pattern inspection apparatus detects the first edge from an image of a pattern to-be-inspected. Next, the pattern inspection apparatus conducts matching of the image of the pattern to-be-inspected and the first reference pattern by comparing the first edge and an edge of the first reference pattern. Since, as a result of the matching, a shift quantity Scan be obtained, and then the first reference pattern is shifted by this shift quantity S. Subsequently the pattern to-be-inspected is inspected by comparing the first edge and the edge of the first reference pattern so shifted. In this first inspection, pattern deformation quantities are obtained and defects are detected. A shift quantity Scan be obtained as one of the pattern deformation quantities. Next, in order to detect the second edge from the pattern image to-be-inspected, the corresponding second reference pattern is shifted by a shift quantity S+S. Using the second reference pattern so shifted, a profile is obtained on the pattern image to-be-inspected and the second edge is detected. Then, by comparing the second edge and the edge of the second reference pattern so shifted, the pattern to-be-inspected is inspected. Also in this second inspection, the pattern deformation quantities are obtained and defects are detected. A shift quantity Scan be obtained as one of the pattern deformation quantities.

Pattern inspection apparatus, pattern inspection method, and recording medium

A method for automatically recognizing a stage position of a feature of a semiconductor wafer comprises the steps of identifying a feature of a semiconductor wafer disposed at a predetermined distance from an alignment mark on the semiconductor wafer and obtaining an electron beam image, an optical image or a differential image thereof of the feature of the semiconductor wafer. A normalized correlation coefficient from the image of the feature is then calculated, and a stage position of the feature of the semiconductor wafer is automatically recognized in accordance with the normalized correlation coefficient.

Scanning electronic microscope and method for automatically observing semiconductor wafer

Using a scanning type electron microscope, a spot where a particle is detected is determined by acquiring the evaluation of detection of particles on the surface of a wafer, etc., based on the coordinate information of a particle spot, by particle detection equipment, from the image within the view, shifting the view from the most probable spot of particle existence to less probable spots in sequence, and manipulating evaluation of detection as follows; supposing that the variance of histogram of the image is .sigma., and that the value N is equal to or more than 3, which is empirically known, and assuming that the spots where the data out of the range of .+-.N.sigma. exist is that of particles detected, pixels of particles are counted. In this manipulation, weighting corresponding to the spot of histogram and weighting corresponding to the mean of intensity of detection at the neighborhood of particles are executed.

Particle analysis method

A method of automatically setting a coordinate conversion factor in which, under the condition where a sample having a simple contour, such as a wafer with a known contour, is installed in a shape observing unit, in order to determine the conversion factor between a coordinate system defined by the contour of the sample and a control coordinate system for an observing position such as a stage coordinate system, the edge position of the contour of the sample is automatically recognized at a high accuracy from a secondary electron picture which has been obtained from the shape observing unit, from the result of which the conversion factor between the sample coordinate system and the stage coordinate system is automatically set.

Growing community of inventors

Tokyo, Japan

Tadashi Kitamura