Fujitsu Corporation

Tadashi Kiriseko

Takeshi Fukuda

Nobuo Iijima

Yoshiharu Mitono

Kazuo Tokitomo

Nobuhisa Shigemi

Toshio Kurahashi

Hideo Onodera

Hiromichi Tani

Yoshiyuki Shibamata

Noriko Soma

Takayuki Toyoda

A continuous semiconductor substrate processing system is operated by a system control structure in accordance with a predetermined processing program. A wafer conveying mechanism conveys wafers to and from each of plural process stations, each of which performs a corresponding process step on semiconductor wafers, to and from a stocker and to and from an inspection unit. Carriers, movable by manual or mechanical structure other than the wafer conveying mechanism, provide for alternative conveying of wafers to and from each of the process stations, the stocker and the inspection station. The system control structure monitors and selectively controls each of the wafer conveying mechanism, the process stations and the stocker and issues instructions for movement of the carriers and monitors the positioning of carriers for selective control of the transfer of wafers and the priority sequence of processing of wafers, to maintain continuous performance of plural process steps on plural lots of semiconductor wafers.

Continuous semiconductor substrate processing system

Automatic identification of each semiconductor wafer during wafer processing is achieved by the invention regardless of layers deposited on a code pattern. The code pattern, preferably, a bar code pattern, is formed on a front surface of the semiconductor wafer, and a light beam including infrared rays is irradiated onto a bottom surface thereof. The infrared rays easily penetrate through the silicon wafer and reflect from the bar code pattern formed on the front surface of the wafer. The reflected beam of infrared rays is received by a detector disposed on a back side of the wafer, and each wafer is identified by decoding the received signal. The bar code pattern can be directly formed by inscribing the wafer surface by a laser beam or inscribing a metal layer deposited thereon.

Method of identifying a semiconductor wafer utilizing a light source and

In an automatic wafer process for gate array integrated circuits, it becomes necessary to identify the wafer every time at the beginning of each process. However, it is difficult for conventional methods to identify the wafer by detecting a bar code pattern because of a low contrast due to reflection of the deposited layers. The present invention provides a method in which the light source, which abundantly includes infrared rays, located on the back side of the wafer and a detector located on the front side thereof. The infrared rays are irradiated onto the wafer easily penetrate the silicon wafer. The infrared rays are received without an effect of reflection due to the deposited layers on the front side of the wafer. The first metallization layer is a very suitable layer to form the bar code pattern, which is easily marked by a laser beam scriber.

Methods for identifying semiconductor wafer with bar code pattern

In an output transistor of transistor-transistor logic (TTL) circuits, an output transistor of TTL is provided with, in a region between a p-type base region and the p-type semiconductor substrate on which a TTL circuit is fabricated, a p.sup.- diffusion which causes carriers stored in the base region when the output transistor is switched from ON state to OFF state to be discharged quickly. When the output transistor is OFF, the p.sup.- diffusion is pinched off and no current flows. Thus, when the output transistor is switched from OFF state to ON state, the output voltage changes sharply. Because of this, the switching speed of the TTL is improved. In another embodiment, a p.sup.- region is formed between a p-type base region and p.sup.+ isolation diffusion, and an n.sup.+ diffusion is formed to cover at least one part of the p.sup.- diffusion and is connected to an n-type collector region. In another embodiment, a p-type base region extends to the p.sup.+ isolation diffusion, and an n.sup.+ diffusion is formed in a region between the base region and the isolation diffusion and is connected to an n-type collector region.

Semiconductor device with a means for discharging carriers

A method of producing a semiconductor device, including a bipolar transistor and a Schottky barrier diode (e.g., an SBD transistor), includes the steps of selectively etching an insulating layer formed on an N-type silicon epitaxial layer so as to form an emitter electrode contact window; and forming a polycrystalline silicon layer on the exposed portion of a P-type base region in the window. The method further includes the steps of introducing N-type impurities into the P-type base region through the polycrystalline silicon layer in the window, selectively etching the insulating layer so as to form a base electrode contact window and a contact window for the electrode of the SBD and carrying out a heat treatment for redistribution of the introduced impurities so as to form an emitter region. An emitter electrode is then formed on the polycrystalline silicon layer and the electrode of the SBD is formed directly on the silicon epitaxial layer.

Method of producing a semiconductor device

In a process for producing a semiconductor device, having a thick silicon oxide layer, on an isolation region, an oxide layer is selectively formed on an area for providing the isolation region of the epitaxial layer. Then an anti-oxidation masking layer is selectively formed on the oxide layer. The semiconductor substrate is selectively oxidized using the anti-oxidation masking layer for forming the thick silicon oxide layer. The anti-oxidation masking layer on the silicon oxide layer, which corresponds to the area for providing the isolation region, is removed and impurities are introduced into the area for providing the isolation region. Then the semiconductor substrate is oxidized in an oxidizing atmosphere so that the impurities are activated to form an isolation region and an oxide layer on the isolation region, the oxide layer having an increased thickness. The thus-obtained thick silicon dioxide layer makes the parasitic capacitance between the conductive lines and the isolation region small.

A system and method for evenly heating semiconductor wafers in a horizontal elongated reaction tube, wherein a furnace surrounding only a part of the length of the reaction tube is caused to move so as to pass along each wafer placed in the reaction tube. The system is especially useful for processing wafers at high temperatures for a short period of time.

Method and apparatus for heating semiconductor wafers

A method for producing a bipolar transistor which has no emitter-base short and which attains a high density of integration. The method comprises the steps of forming a polycrystalline silicon layer on an anti-oxidation masking layer formed on a base region, selectively etching the polycrystalline silicon layer to form an opening, introducing impurities into the base region to form an emitter region, converting the polycrystalline silicon layer into an oxide layer whereby the size of the opening is reduced, selectively etching the anti-oxidation masking layer to form an emitter electrode opening, and forming electrodes.

Method for producing a bipolar transistor utilizing an oxidized

In a method of manufacturing semiconductor devices, liquid glass is applied to the substrate of a semiconductor device to cover the upper surface of a film of photoresist formed on a conductor layer of the substrate and used as an etching mask for patterning the conductor layer. The substrate is baked at a sufficiently high temperature to harden the liquid glass and deform and shrink the photoresist film to expose the sides of such film. The photoresist film is removed. The hardened liquid glass on the photoresist film is simultaneously removed by lift off.

Growing community of inventors

Kanagawa, Japan

Tadashi Kiriseko