Toshiba America Electronic Components, Inc.

Tadashi Iijima

Yoshiaki Shimooka

An interconnect method in a semiconductor device may include a step of examining various regions of an inter layer dielectric to identify regions having high densities or concentrations of trench features. A cap insulator layer may be added to the dielectric to assist in outgassing of absorbed impurities from the dielectric, but may be removed from the high density areas to allow the lower density areas to increase outgassing. The lower density areas may then compensate for increased outgassing on the high density areas due to the trench features, and may result in an overall device with a more stable dielectric constant across the device.

Interconnect structure and method for semiconductor device

A semiconductor device and a method for making the semiconductor device having a barrier layer in a via hole region and a barrier layer in a via line region. The barrier layer in the via line region is initially thicker than the barrier layer in the via hole region, prior to being etched during an etching process due to varying selectivity of etching rates between the via hole region and the via line region.

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Yorktown Heights, NY, United States of America

Tadashi Iijima