Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Tadashi Iguchi

Hiroaki Tsunoda

Megumi Ishiduki

Murato Kawai

Hisashi Kato

Takuya Inatsuka

Yoshiaki Himeno

Masao Iwase

Daigo Ichinose

Toru Matsuda

Koichi Matsuno

Hisashi Watanobe

Fumitaka Arai

Ryota Katsumata

Masaru Kidoh

Yasuhiko Matsunaga

Makoto Sakuma

Hirohisa Iizuka

Yoshihiro Yanai

Natsuki Fukuda

Riichiro Shirota

Mitsuru Sato

Mitsuhiro Noguchi

Atsushi Fukumoto

Seiichi Aritome

Seiichi Mori

Kazuyuki Higashi

Masahiro Kiyotoshi

Makoto Mizukami

Kazuhiro Shimizu

Takashi Izumida

Hiroaki Hazama

Masaki Kondo

Yoichi Minemura

Fumiki Aiso

Yoshihiro Uozumi

Kazuhito Narita

Kenji Aoyama

Eiji Ito

Katsunori Yahashi

Kiyohito Nishihara

Kenji Gomikawa

Masahisa Sonoda

Hirokazu Ishida

Kazuyuki Masukawa

Eiji Sakagami

Moto Yabuki

Seiichi Omoto

Yoshihiro Akutsu

Tsuneo Uenaka

Junichi Hashimoto

Shoichi Watanabe

Katsuhiro Ishida

Osamu Yamane

Naoki Koido

Gaku Sudo

Ryuichi Kamo

Takuya Mizutani

Shuichi Kuboi

Kunihiro Terasaka

Hiromitsu Iino

Masanobu Baba

Soichiro Kitazaki

A semiconductor memory device includes a substrate including a first region and a second region, a plurality of first conductive layers, a first semiconductor layer disposed in the first region, an electric charge accumulating layer, a contact electrode disposed in the second region and connected to one of the plurality of first conductive layers, and a plurality of first structures and a plurality of second structures disposed in the second region. The first structure includes a second semiconductor layer opposed to the plurality of first conductive layers and including a semiconductor material in common with the first semiconductor layer, and a first insulating layer disposed between the plurality of first conductive layers and the second semiconductor layer and including an insulating material in common with the electric charge accumulating layer. The second structure does not include the semiconductor material or the insulating material.

Semiconductor memory device

A semiconductor storage device includes a substrate having a memory region and a hook-up region arranged in a first direction and memory structures arranged in a second direction. The memory structures include conductive layers arranged in a third direction and extending in the first direction over the memory region and the hook-up region and contact electrodes provided in the hook-up region and extending in the third direction to have an outer peripheral surface surrounded, each contact electrode being connected to any of the conductive layers. The hook-up region includes a first region, with a first contact electrode and a second contact electrode, and a second region, with a third contact electrode and a fourth contact electrode. In the third direction, a first average length of the first and second electrodes is equal to a second average length of the third and fourth contact electrodes.

Semiconductor storage device

A method of producing a semiconductor memory device includes, when three directions crossing each other are set to first, second, and third directions, respectively, laminating a plurality of first laminates and a plurality of second laminates on a semiconductor substrate in the third direction. The method further includes forming ends of the plurality of first laminates in shapes of steps extending in the first direction, and forming ends of the plurality of second laminates in shapes of steps extending in both directions of the first direction and the second direction.

Semiconductor memory device and production method thereof

According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.

A semiconductor memory device includes a substrate, conductive layers arranged in a first direction and extend in a second direction, a semiconductor layer extending in the first direction and opposed to the conductive layers, and n contact electrode regions arranged in a third direction. The n is a power of 2. The contact electrode region includes contact electrodes arranged in the second direction. The conductive layers include a first conductive layer and a second conductive layer that is an n-th conductive layer counted from the first conductive layer. The contact electrodes include a first contact electrode connected to the first conductive layer, a second contact electrode connected to the second conductive layer, and a third contact electrode disposed between them. The first contact electrode, the second contact electrode, and the third contact electrode are arranged in the second direction or the third direction.

A semiconductor storage device includes: a substrate having a front surface; a plurality of conductive layers arranged in a first direction, the first direction intersecting the front surface of the substrate; a plurality of memory cells connected to the plurality of conductive layers; a contact electrode extending in the first direction and connected to one of the plurality of conductive layers; and an insulating structure extending in the first direction, the insulating structure connected to an end portion of the contact electrode on one side of the contact electrode in the first direction, and penetrating the plurality of conductive layers.

A memory device according to an embodiment includes: a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer parallel to a first direction and a second direction perpendicular to the first direction, and stacked in a third direction perpendicular to the first direction; a first, electrode connected to the first conductive layer; a second electrode connected to the second conductive layer; a third electrode connected to the third conductive layer; and a fourth electrode connected to the fourth conductive layer. The third conductive layer and the fourth conductive layer are not provided between the first electrode and the second electrode. The fourth conductive layer is not provided between the second electrode and the third electrode. A region without the second conductive layer is provided between the second electrode and the third electrode.

Memory device and method for manufacturing the same

A semiconductor memory device according to an embodiment includes a memory cell array that includes memory cells and a plurality of first conducting layers. The memory cells are arrayed in a three-dimensional manner. The first conducting layers are connected to the memory cells and are arrayed in a laminating direction. Stepped wiring portion includes a plurality of second conducting layers. The plurality of second conducting layers connect the first conducting layers and external circuits. At least one of the plurality of second conducting layers includes a contact formation area on a top surface thereof in the stepped wiring portion positioned on the first side portion side. Other ones of the plurality of second conducting layers includes a contact formation area on a top surface thereof in the stepped wiring portion positioned on the second side portion side.

Semiconductor memory devices including a memory cell array and stepped wiring portions, and manufacturing methods thereof

A semiconductor memory device according to an embodiment includes a memory cell array configured to have a memory string obtained by connecting first selection transistors, memory transistors, and second selection transistors in series. When three directions crossing each other are set to first, second, and third directions, respectively, the memory cell array has first conductive layers to be control gates of the first selection transistors, second conductive layers to be control gates of the memory transistors, and third conductive layers to be control gates of the second selection transistors, which are laminated in the third direction. Ends of the first conductive layers and ends of the third conductive layers are formed in shapes of steps extending in the first direction and ends of the second conductive layers are formed in shapes of steps extending in both directions of the first direction and the second direction.

According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a stacked body alternately stacked with a plurality of members and a plurality of intermediate bodies having materials different from materials of the plurality of members, processing an end portion of at least two layers of the plurality of members sequentially in a stacking direction of the stacked body, and forming a step-wise step stacked with the plurality of members and the plurality of intermediate bodies, forming a plurality of side wall films contacting the step and making the end portion of the plurality of members in a step-wise. The making the end portion of the plurality of members in a step-wise includes retreating a portion of the plurality of members, the portion separated from the plurality of side wall films and exposed from the stacked body.

Semiconductor device and method for manufacturing same

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Yokkaichi, Japan

Tadashi Iguchi