Kabushiki Kaisha Toshiba

Toshiba Electronic Devices & Storage Corporation

Tadashi Arai

Tetsuro Itakura

Takashi Ueno

Hiroshi Yoshida

Mikio Koyama

Takafumi Yamaji

Manabu Yamada

Makoto Arai

Masaki Nishikawa

Shoji Ootaka

Shigeyasu Iwata

Mamoru Tanaka

Takeshi Murasaki

Akio Maeda

An isolation amplifier of an embodiment includes: a primary circuit including an encoder configured to encode an input signal and output the encoded input signal and an anomaly detection circuit configured to detect anomaly having occurred to the input signal and generate a detection signal; an isolation unit configured to insulate the primary circuit from a secondary circuit; an output circuit configured to generate an output signal corresponding to the input signal; and an anomaly-input sensing-output circuit configured to generate an output signal from the secondary circuit by changing the output signal from the output circuit based on the detection signal.

Isolation amplifier and anomaly state detection device

A variable gain amplifier device comprises a variable gain amplifier circuit which amplifies a difference between an input signal and a feedback signal to output an output signal, a feedback circuit which supplies the feedback signal to the variable gain amplifier circuit, and a controller which controls the variable gain amplifier circuit and the feedback circuit to decrease a cutoff frequency of the feedback circuit according to increase of a gain of the variable gain amplifier circuit or vice versa.

Variable gain amplifier

A variable gain amplifier comprises a main amplifier circuit whose gain is controllable and which amplifies a difference signal between an input signal and a feedback signal, a feedback amplifier circuit whose gain is controllable and which amplifies an output signal of the main amplifier circuit, and a gain control circuit which complementarily control the gain of the main amplifier circuit and the gain of the feedback amplifier circuit.

A gain cell circuit includes a logarithmic transformation circuit. The logarithmic transformation circuit includes a pair of first and second transistors, each of which has first and second current carrying electrodes and a control electrode. The control electrodes of the first and second transistors are coupled to input terminals of the logarithmic transformation circuit. The logarithmic transformation circuit further includes third and fourth transistors coupled to the first and second transistors. The third and fourth transistors have control electrodes serving as output terminals of the logarithmic transformation circuit, first current carrying electrodes connected at first and second circuit nodes to the second current carrying electrodes of the first and second transistors, and second current carrying electrodes coupled to a power supply voltage. The logarithmic transformation circuit further includes an impedance element connected between the first and second nodes, and level-shift circuits connected to the second current carrying electrodes of the first and second transistors and to the control electrodes of the third and fourth transistors.

Logarithmic transformation circuitry for use in semiconductor integrated

Biological intestinal antiseptics

Growing community of inventors

Yokohama, Japan

Tadashi Arai