Panasonic Corporation

Panasonic Intellectual Property Corporation of America

Tadao Tanikawa

Katsushige Amano

Masahiko Saito

Ryo Yokoyama

Toshiaki Takeuchi

Masashi Sugiyama

Ryota Miyazaki

Teruo Kamiyama

Takuya Kondoh

Katsuhiro Arinobu

A virtual machine system that restricts use of confidential information only to the case where an authentication has resulted in success. The virtual machine system includes first virtual machine, second virtual machine, and hypervisor. The first virtual machine includes: storage unit storing confidential information; and authentication unit configured to perform authentication and notify the hypervisor of result of the authentication. The second virtual machine uses virtual device that is virtualized storage device. When having received authentication result indicating authentication success from the authentication unit, the hypervisor enables the second virtual machine to access, as substance of the virtual device, storage area storing the confidential information, and when not having received the authentication result indicating the authentication success from the authentication unit, the hypervisor disables the second virtual machine from accessing the storage area storing the confidential information.

Virtual machine system, confidential information protection method, and confidential information protection program

A virtual machine control apparatuscontrols execution of a first type virtual machine Aand a second type virtual machine. The first type virtual machine Aincludes a start detection unitwhich detects an operation in the first type virtual machine Ato start usage of a device (external storage device). The first type virtual machine Aalso includes a start signal output unitwhich outputs a start signal when the start detection unitdetects the operation to start usage of the device. The second type virtual machineincludes a control unit (external storage device driver) which, when the start signal output unitoutputs the start signal while the device is in set in a low power mode (electrical power set to off), sets the device in a normal mode (electrical power set to on).

Virtual machine control apparatus and virtual machine control method

The present invention relates to a virtual machine system that includes a plurality of processors and executes a plurality of virtual machines in parallel with use of the plurality of processors. An aim thereof is to suppress power consumption without sacrificing the performance of the virtual machine system. When there are at least two processors that do not have any virtual machines allocated thereto, one of the at least two processors is supplied with power so as to be placed in a standby state, and a remaining one or more of the at least two processors are not supplied with power.

Virtual computer system, virtual computer control method and accumulation circuit

When a process judging unit judges that a target process is a protected process, a key judging unit judges whether a target key that is a key generated by a key generating unit is a first key or a second key. When the key judging unit judges that the target key is the first key, a VM communication managing unit notifies the target process of a memory ID of a protected memory region corresponding to the first key. When the process judging unit judges that the target process is an unprotected process, a key transforming unit transforms the target key from the first key to the second key based on the key transformation rule. An HV communication managing unit notifies the target process of a memory ID of an unprotected memory region corresponding to the second key.

Virtual computer system having a first virtual computer that executes a protected process, a second virtual computer that executes an unprotected process, and a hypervisor that controls the first and second virtual computers

A computer system enables two virtual machines with use of two virtual CPUs. The computer system includes a CPU that is allocated to the virtual CPU when the virtual CPU performs computer processing of the virtual machine other than timer processing; a tick CPU that is dedicated to timer processing and is allocated to the virtual CPU upon receiving an interrupt request (tick interrupt) for causing the virtual CPU to perform timer processing of the virtual machine; and interrupt controller that issues the tick interrupt to the tick CPU.

Computer system for controlling the execution of virtual machines

An instruction detecting section () detects whether or not there is any succeeding instruction executable regardless of an order based on a data dependency relationship between a presently executed instruction and a succeeding instruction following the presently executed instruction. A clock switch judging section () receives notification of the start and end of a memory stall, determines whether or not a memory stall is occurring, and judges whether to switch a clock signal to be supplied to a CPU () to a low clock signal () or to stop the clock signal based on a detection result of the instruction detecting section () if it is judged that the memory stall is occurring. A clock switching section () switches the clock signal based on judgment by the clock switch judging section (). By this construction, power consumption can be reduced without reducing performance.

Clock control device, clock control method, clock control program and integrated circuit

A job control information storing section stores execution conditions under which execution of tasks is started, and an execution order of the tasks. A job executing section executes the tasks. A job execution administering section monitors a state of the task being executed to detect the task whose state is shifted to a process standby state of waiting for a response from another one of the tasks, based on the execution conditions, and responds to a request of executing the another task from the task whose state is shifted, in response to accepting the request from the task whose state is shifted. A virtual task generating section generates a virtual task as a copy of the task whose state is detected to be shifted. A virtual task registering section adds the virtual task to the execution order to concurrently execute the virtual task with the task whose state is shifted.

Generation and concurrent execution of a virtual task in an execution order determining system

The interrupt level storing unit () stores one or more interrupt levels indicating the priority of a generated interrupt and stores the interrupt level having the highest priority among the stored interrupt levels as a second interrupt mask level. The second interrupt type determination unit () sets an interrupt level corresponding to the interrupt type of a newly generated interrupt. The priority determination unit () notifies the interrupt to the virtual machine control unit () when the interrupt level of the newly generated interrupt is higher than the stored second interrupt mask level. As a result, the priority of the virtual machine can be determined according to the task priority and the switching of virtual machines can be adequately controlled even if the virtual machines cannot notify the task priority.

Virtual machine control device, virtual machine control program, and virtual machine control circuit for managing interrupts of plural virtual machines

An access monitoring section () obtains access information including an address conforming to an address stored in a monitoring address setting section () from an access signal output from a CPU () to a peripheral device (). An access judging section () compares the access information received from the access monitoring section () and the last access information stored in an access storing section (), and stores the obtained access information in the access storing section () and requests the transmission of an exception generation notification to an exception generating section () when the received access information is different from the last access information while excluding the last access information stored in the access storing section () from access information to be compared when the received access information is the same as the last access information. By this construction, throughput can be reduced at the time of emulation and the peripheral device can be efficiently emulated.

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Osaka, Japan

Tadao Tanikawa