Fujitsu Corporation

Fujitsu Semiconductor Limited

Tadao Aikawa

Yasuharu Sato

Takaaki Suzuki

Shinya Fujioka

Hiroyuki Kobayashi

Masao Taguchi

Yasurou Matsuzaki

Waichirou Fujieda

Hirohiko Mochizuki

Hitoshi Ikeda

Atsushi Hatakeyama

Masafumi Yamazaki

Shusaku Yamaguchi

Masato Takita

Masahiro Niimi

Yoshihiro Takemae

Hiroyoshi Tomita

Toshiya Uchida

Masao Nakano

Hiroshi Miyazaki

Takayuki Nagasawa

Koichi Nishimura

Noriyuki Tokuhiro

Waichiro Fujieda

Hiroshi Miyake

In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.

Semiconductor apparatus having a large-size bus connection

A method for compensating for semiconductor device resistance is disclosed that includes the step of realizing a resistance equal to a desired resistance by one of combinations of multiple semiconductor devices. This step includes the step of sequentially selecting two or more of the semiconductor devices to be combined, and thereby sequentially changing a resistance realized by the selected two or more of the semiconductor devices to be combined.

Resistance compensation method, circuit having a resistance compensation function, and circuit resistance test method

A semiconductor memory that reduces power consumed by a CAM. A storage circuit has stored a plurality of patterns of information indicative of whether to activate each memory word block. If specification information for specifying a predetermined pattern from among the plurality of patterns of information which has been stored in the storage circuit is input, an activation circuit activates each content addressable memory word block according to a specified pattern. If data to be retrieved is input, a specification circuit specifies a content addressable memory word which has stored data corresponding to the data to be retrieved from among a group of content addressable memory words activated by the activation circuit. As a result, activation will be performed by the content addressable memory word block. Therefore, by activating only necessary content addressable memory words, consumption of power can be reduced.

Semiconductor memory

A semiconductor device including a parallel to serial conversion circuit that receives first through n data (where n is an integer greater than or equal to 2), together with (n&plus;1) data, in parallel to each other, and that outputs the first through n data in series in this order via first through n paths in a first operating mode, while it outputs the (n&plus;1)th data via one of the second through n paths in a second operation mode. An output control circuit is connected to the parallel to serial conversion circuit via the first through nth paths, the output control circuit successively outputting the first through n data in the first operating mode, and outputting only the (n&plus;1) data supplied from the parallel to serial conversion circuit in the second operating mode.

Semiconductor integrated circuit device capable of outputting leading data of a series of multiple burst-readout data without delay

A semiconductor memory circuit includes a plurality of memory cell arrays arranged in rows and columns. A decoder circuit selects a predetermined number of memory cell arrays from among the plurality of the memory cell arrays. Sense amplifiers sense data read from selected memory cell arrays. The plurality of memory cell arrays are grouped into a first type of memory cell arrays each having a redundant memory cell and a second type of memory cell arrays each having no redundant memory cell.

Semiconductor memory circuit having selective redundant memory cells

The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and said plurality of sense-amplifiers.

Semiconductor memory device

The present invention is a memory circuit for writing prescribed numbers of bits of write data, determined according to the burst length, in response to write command, comprising: a first stage for inputting, and then holding, row addresses and column addresses simultaneously with the write command; a second stage having a memory core connected to the first stage via a pipeline switch, wherein the row addresses and column addresses are decoded, and word line and sense amps are activated; a third stage for inputting the write data serially and sending the write data to the memory core in parallel; and a serial data detection circuit for generating write-pipeline control signal for making the pipeline switch conduct, after the prescribed number of bits of write data has been inputted. According to the present invention, in an FCRAM exhibiting a pipeline structure, the memory core in the second stage can be activated after safely fetching the write data in the burst length. When writing successively or reading successively, moreover, the command cycle can made short irrespective of the burst length.

Semiconductor memory device operating in synchronization with a clock signal for high-speed data write and data read operations

A semiconductor memory device outputs data in synchronization with an external clock signal. The semiconductor memory device comprises a first frequency divider dividing a frequency of the external clock signal supplied thereto so as to generate a first internal clock signal; a delay circuit delaying the external clock signal; a second frequency divider dividing a frequency of a signal supplied from the delay circuit so as to generate a second internal clock signal; and a data control unit outputting the data according to the first internal clock signal and the second internal clock signal.

Semiconductor memory device outputting data according to a first internal clock signal and a second internal clock signal

A semiconductor memory device that performs a flash write operation without increasing the circuit area. Column selection lines CL -CL extend parallel to word lines at locations corresponding to where column gates are formed. During a flash write mode, the subcolumn decoder simultaneously selects the column selection lines. This writes cell information to every memory cell connected to the selected word line.

Method for writing data to semiconductor memory and semiconductor memory

According to an aspect of the present invention, a memory device having a plurality of banks carries out bank interleaving by use of a plurality of common data buses, the number of which is less than the number of the banks. The present invention enables the data to be read more rapidly while suppressing the increase of the chip area. According to the present invention, there is provided a memory device having a plurality of banks each including a plurality of memory cells, and reading or writing data from or into the memory cells in synchronism with a clock signal, the memory device comprising: a sense amplifier disposed on each of the plurality of banks, for amplifying data read from the memory cells; a plurality of common data buses shared by the plurality of banks, the number of the common data buses being less than the number of the banks; and a switching circuit disposed on each of the plurality of banks, for feeding or receiving data of the each bank to or from the plurality of common data buses; wherein read or write of data of the plurality of banks is made through successive selection of the plurality of common data buses by the switching circuit.

Memory device with a plurality of common data buses

A clock pulse generator generates a plurality of clock pulses which has different phases during one cycle of a reference clock signal supplied from the exterior. A timing setting circuit sets a latency, which is a number of clock cycles from a start of a read operation to an output of read data, at a number which is divisible by one n-th (n&equals;2, 3, 4 . . . ) of a cycle of the reference clock signal and outputs latency information according to the set latency. An output controlling pulse switching circuit respectively outputs each of the clock pulses as a predetermined output controlling pulse in accordance with the latency information. In other words, a plurality of the output controlling pulses are switched according to the latency information. In synchronization with each of the output controlling pulses, a data outputting circuit sequentially and respectively converts parallel data, read from a plurality of memory cells stored with data, into serial data and respectively outputs the converted serial data during the predetermined period according to the latency. No matter what timing of the reference clock signal the latency might be set at, therefore, the serial data can be reliably outputted without switching the parallel data. The data are outputted at high speed because the parallel data need not be switched.

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Kawasaki, Japan

Tadao Aikawa