Renesas Technology Corp.

Hitachi, Ltd.

Hitachi Chemical Company, Ltd.

Tadanori Segawa

Toshiya Satoh

Asao Nishimura

Masahiko Ogino

Akira Nagai

Ichiro Anjo

Takao Miwa

Takumi Ueno

Takashi Naito

Hiroki Yamamoto

Ichiro Anjoh

Akihiro Yaguchi

Ken Takahashi

Toshiaki Ishii

Shuji Eguchi

Takao Ishikawa

Nobutake Tsuyuno

Hiroyoshi Kokaku

Takashi Namekawa

Yoshihide Yamaguchi

Atsushi Kazama

Hiroyuki Tenmei

Yasutaka Suzuki

Shigehisa Motowaki

Osamu Shiono

Kunihiko Nishi

Masatsugu Ogata

Hiroshi Suzuki

Shunichi Numata

Hidetoshi Abe

Shigeo Suzuki

Tatsuo Kawata

Daigoro Kamoto

Toshiya Sato

Daigorou Kamoto

Masahiro Kitamura

A wiring glass substrate includes a glass substrate formed of glass and having a plurality of holes formed at predetermined positions, bumps so formed as to be connected to a conductive material filling the holes and wirings formed on a surface opposite to a surface having the bumps formed thereon and electrically connecting a plurality of connection terminals arranged in intervals different from intervals of the holes to the conductive material. The shape of the conductive material is porous and porous electrodes are bonded to the inner wall surfaces of the holes by an anchor effect to increase the strength of the glass substrate.

Wiring glass substrate for connecting a semiconductor chip to a printed wiring substrate and a semiconductor module having the wiring glass substrate

The present invention is a semiconductor device having the semiconductor element obtained by cutting a semiconductor wafer with the electrode pad formed on one side along a scribe line, a semiconductor element protective layer on the semiconductor element which has a opening on the pad, a stress cushioning layer on the layer which has the opening on the pad, a lead wire portion reaching the layer from the electrode pad via the openings, external electrodes on the lead wire portion, and the conductor protective layer on the layers, the layer and the conductor protective layer forming the respective end faces on the end surface of the semiconductor element inside the scribe line and exposing the range from the end face of the end surface to the inside of the scribe line.

Semiconductor device and manufacturing method thereof

Semiconductor devices,-semiconductor wafers, and semiconductor modules are provided: wherein the semiconductor device has a small warp; damages at chip edge and cracks in a dropping test are scarcely generated; and the semiconductor device is superior in mounting reliability and mass producibility. The semiconductor devicecomprising: a semiconductor chipa porous stress relaxing layerprovided on the plane, whereon circuits and electrodes are formed, of the semiconductor chip; a circuit layerprovided on the stress relaxing layer and connected to the electrodes; and external terminalsprovided on the circuit layer; wherein an organic protecting filmis formed on the plane, opposite to the stress relaxing layer, of the semiconductor chip, and respective side planes of the stress relaxing layer, the semiconductor chipand the protecting filmare exposed outside on a same plane.

Semiconductor device, semiconductor wafer, semiconductor module, and a method of manufacturing semiconductor device

A semiconductor device having a semiconductor element is obtained by cutting a semiconductor wafer, having an electrode pad formed on one side thereof, along a scribe line. The semiconductor device has a semiconductor element protective layer on the semiconductor element so as to form an opening above the pad, a stress cushioning layer on the layer so as to form an opening on the pad, a lead wire portion reaching the layer from the electrode pad via the openings, external electrodes on the lead wire portion, and a conductor protective layer on the layer. The layer, the layer, and the conductor protective layer form respective end faces on the end surface of the semiconductor element inside the scribe line and expose a surface of the semiconductor element from the end face of the end surface to a point inside of the scribe line, thereby to expose the scribe line.

Semiconductor devices, semiconductor wafers, and semiconductor modules are provided, wherein: the semiconductor device has a small warp; damage at the chip edge and cracks occurring in a dropping test are scarcely generated; and the semiconductor device is superior in mounting reliability and mass producibility. The semiconductor includes a semiconductor chip; a porous stress relaxing layerprovided on the plane, whereon circuits and electrodes are formed, of the semiconductor chip; a circuit layerprovided on the stress relaxing layer and connected to the electrodes; and external terminalsprovided on the circuit layer; wherein an organic protecting filmis formed on the plane, opposite to the stress relaxing layer, of the semiconductor chip, and respective side planes of the stress relaxing layer, the semiconductor chip, and the protecting filmare exposed outside on the same plane.

A miniature semiconductor apparatus is outstanding in reflow resistance, temperature cycle property, and PCT resistance corresponding to high density packing, high densification, and speeding up of processing. The semiconductor apparatus has at least one stress cushioning layer on a semiconductor element with an electrode pad formed, having a conductor on the stress cushioning layer, having a conductor for conducting the electrode pad and conductor via a through hole passing through the stress cushioning layer between the electrode pad and the conductor, having an external electrode on the conductor, and having a stress cushioning layer in an area other than the area where the external electrode exists and a conductor protection layer on the conductor, wherein the stress cushioning layer includes crosslinking acrylonitrile-butadiene rubber having an epoxy resin which is solid at 25&deg; C. and a carboxyl group.

Semiconductor apparatus having stress cushioning layer

A manufacturing method makes it possible to produce a semiconductor apparatus which is outstanding in mounting reliability at a high manufacturing yield rate. A semiconductor apparatus, in which, on the surface of a semiconductor chip with a circuit and an electrode formed thereon, a stress cushioning layer is provided, except for a part where the electrode is, has a wiring layer connected to the electrode on the stress cushioning layer, an external protection film on the wiring layer and stress cushioning layer, a window where a part of the wiring layer is exposed at a predetermined location of the external protection film, and an external electrode which is electrically connected to the wiring layer via the window. The stress cushioning layer, wiring layer, conductor, external protection film, and external electrode are formed on the inside of the end of the semiconductor chip.

Semiconductor apparatus and a manufacturing method thereof

A resin encapsulated semiconductor device sealed with an epoxy resin molding material particularly containing a brominated epoxy resin as a flame retardant with the bromine content of 0.5% by weight or less, antimony oxide as a flame retardant in an amount of 2.0% by weight or more and a quaternary phosphonium tetrasubstituted borate as a curing accelerator is excellent in connection reliability at Au/Al junctions and heat resistance.

Resin encapsulated semiconductor device

Resin encapsulated electronic devices are provided by encapsulating so-called flat-shaped, plate-like, or angular-shaped electronic devices with a resin composition containing rubber-like particles preferably having an average particle size of 150 .mu.m or less. In the course of production of said resin encapsulated electronic devices, no crack is produced in the electronic devices by the stress from the outside, and after production, said resin encapsulated electronic devices are amazingly lessened in formation of cracks by thermal stress and have high reliability.

Resin encapsulated electronic devices

Growing community of inventors

Hitachi, Japan

Tadanori Segawa