Samsung Electro-mechanics Co., Ltd.

Samsung Electronics Co., Ltd.

Tadamasa Murakami

Tsuyoshi Sugiura

Atsuya Yokoi

Toshihiro Kitajima

Toshihiko Yoshimasu

Edwardo Murakami

An electronic device is provided. The electronic device includes an earphone including a first impedance component, a signal generator configured to output a first alternating current (AC) signal, a first circuit including at least one first analog device having an impedance component electrically coupled to the first impedance component, and configured to receive the first AC signal and output a first detection signal including a voltage component corresponding to the first impedance component, and at least one processor configured to generate at least one piece of biometric information, based on the first detection signal, and output the at least one piece of biometric information.

Electronic device including earphone, and method of controlling the electronic device

A power amplifier includes a first bias circuit including a first and third transistor, a first sub-bias circuit, and an amplifying circuit including a fourth transistor. In the first bias circuit, a second terminal of the first transistor and a second terminal of the first sub-bias circuit are grounded, a control terminal of the first transistor is connected to a control terminal of the first sub-bias circuit, a first terminal of the first sub-bias circuit is connected to a constant voltage terminal, a first terminal of the first transistor is connected to a second terminal of the third transistor, a first terminal of the third transistor is connected to a control terminal of the third transistor. The amplifying circuit amplifies an input signal power based on a first bias signal from the first bias circuit to a control terminal of the fourth transistor.

Power amplifier

An element can be prevented from being damaged even when a high level signal is input to an integrated circuit having a variable capacitance element whose capacitance is variable by digital signal control. There is provided an integrated circuit including b sub-circuits (b is an integer equal to or greater than 1) that are connected in series between a first terminal and a second terminal and have capacitance 2times larger than predetermined unit capacitance. The b-th sub-circuit includes 2configurations, which are connected in parallel, each including at least two capacitors connected in series and at least two stacked switch elements. At least the two stacked switch elements are operated to all switched for each sub-circuit, and at least one switch element of at least the two stacked switch elements is provided between at least the two capacitors.

Integrated circuit and wireless communication apparatus

According to embodiments of the present invention, an over-input signal may be limited to be within a range between adjustable upper limit voltage and lower limit voltage while suppressing deterioration of a noise figure. An amplifier circuit includes an input transistor; an input transistor; a resistor element having a first terminal connected to a gate of the input transistor and a second terminal connected to a bias voltage; and a protective circuit connected to the gate of the input transistor and limiting an input to the gate of the input transistor to be within a range between an upper limit voltage and lower limit voltage adjustable based on the bias voltage.

Amplifier circuit

There is provided a CMOS integrated circuit capable of avoiding deterioration of NF characteristic and achieving a high degree of linearity in the case in which an LNA circuit is formed on an SOI substrate and an LAN circuit is formed in a bulk CMOS process. The CMOS integrated circuit includes a field effect transistor having a gate electrode connected to a signal input terminal, a drain electrode connected to a power terminal, and a source electrode connected to a ground terminal, wherein the field effect transistor is formed on the SOI substrate and a connection between a body potential and a potential lower than a source potential are formed by a resistor element. The deterioration of NF characteristic can be avoided and a high degree of linearity can be achieved by using this CMOS integrated circuit.

CMOS integrated circuit and amplifying circuit

The amplifying circuit includes: an input transistor having a gate electrode connected to a signal input terminal inputting a wireless signal, a drain electrode connected to a power supply terminal, and a source electrode connected to a ground terminal; a first switch installed between the signal input terminal and the gate electrode; and a second switch installed between the power supply terminal and the drain electrode, wherein the input transistor has a predetermined bias voltage applied to the gate electrode thereof to simultaneously turn the first and second switches on during reception of the wireless signal and simultaneously turn the first and second switches off while applying the predetermined bias voltage to the gate electrode during transmission of the wireless signal.

Growing community of inventors

Yokohama, Japan

Tadamasa Murakami