Kabushiki Kaisha Toshiba

Nikon Corporation

Shin-etsu Handotai Co., Ltd.

Kabushiki Kaisha Tosbhia

Tadahito Fujisawa

Soichi Inoue

Masafumi Asano

Satoshi Tanaka

Koji Hashimoto

Takashi Sato

Kyoko Izuha

Toshiya Kotani

Shoji Mimotogi

Takashi Obara

Shinichi Ito

Keiji Horioka

Tsuneyuki Hagiwara

Takeshi Ito

Hiromitsu Mashita

Shuichi Tamamushi

Makoto Kobayashi

Shin-ichi Ito

Kenichi Kodama

Yuko Kono

Masashi Ichikawa

Kei Hayasaki

Ichiro Mori

Akiko Mimotogi

Ayako Nakano

Takumichi Sutani

Atsushi Maesono

Takuya Futatsuyama

Kenji Kawano

Tsuyoshi Shibata

Takashi Sakamoto

Hiroshi Nomura

Kazuya Sato

Eishi Shiobara

Tatsuhiko Higashiki

Yasunobu Kai

Yukiyasu Arisawa

Minoru Inomoto

Daizo Mutoh

According to one embodiment, an exposure control apparatus includes exposure setting unit that performs an exposure setting of setting an exposure shot as a shot that is exposed or a shot that is not exposed based on height information on a height of a substrate in the exposure shot arranged in a substrate peripheral portion, and an exposure instructing unit that outputs an exposure instruction to the shot that is exposed and an instruction to skip an exposure to the shot that is not exposed.

Exposure control apparatus, manufacturing method of semiconductor device, and exposure apparatus

A reticle set, includes a first photomask having a circuit pattern provided with first and second openings provided adjacent to each other sandwiching a first opaque portion, and a monitor mark provided adjacent to the circuit pattern; and a second photomask having a trim pattern provided with a second opaque portion covering the first opaque portion in an area occupied by the circuit pattern and an extending portion connected to one end of the first opaque portion and extending outside the area when the second photomask is aligned with a pattern delineated on a substrate by the first photomask.

Reticle set, method for designing a reticle set, exposure monitoring method, inspection method for reticle set and manufacturing method for a semiconductor device

A photo mask formed with patterns to be transferred to a substrate using an exposure apparatus, the photo mask comprising a pattern row having three or more hole patterns surrounded by a shielding portion or a semitransparent film and arranged along one direction, and an assist pattern surrounded by the shielding portion or semitransparent film and having a longitudinal direction and a latitudinal direction, the assist pattern being located at a specified distance from the pattern row in a direction orthogonal to the one direction, the longitudinal direction of the assist pattern being substantially parallel with the one direction, the longitudinal length of the assist pattern being equivalent to or larger than the longitudinal length of the pattern row, the assist pattern being not transferred to the substrate.

Photo mask, exposure method using the same, and method of generating data

A semiconductor device includes a semiconductor substrate, and a circuit pattern group comprising at least N (&#x2267;2) circuit pattern on the semiconductor substrate, at least one vicinity of end portion among the at least of N circuit patterns including a connection area to electrically connect to a circuit pattern in another circuit pattern group different from the circuit pattern group, the at least N wirings pattern including a circuit pattern Nand at least one circuit pattern Ni (i&#x2267;2) arranged in one direction different from longitudinal direction of the circuit pattern Nthe at least one circuit patterns Ni having larger i being arranged at further position away from the circuit pattern Nand in terms of a pattern including the connection area among the at least of Ni circuit patterns, the larger the i, the connection area being arranged at a further position in longitudinal direction.

Semiconductor device, method for making pattern layout, method for making mask pattern, method for making layout, method for manufacturing photo mask, photo mask, and method for manufacturing semiconductor device

According to this invention, the NAND type flash memory of high reliability is realized. It provides a semiconductor memory device comprising: a plurality of memory cells; a plurality of word lines formed by a first gate wiring layer; a plurality of first transistors for providing voltages to said word lines; and electrical connections for connection said word lines and sources or drains of said first transistors, said electrical connections being formed of both first wirings of a first wiring layer formed above said first gate wiring layer and second wirings of a second wiring layers formed above said first wiring layer.

Semiconductor memory device

A pattern layout for forming an integrated circuit includes a first device pattern, a second device pattern, and an auxiliary pattern. The first device pattern includes a line and a space alternately arrayed on a fixed pitch having regular intervals in a first direction. The second device pattern is disposed on the fixed pitch and separated from the first device pattern in the first direction. The second device pattern has a pattern width an odd-number times larger than the regular intervals of the fixed pitch, wherein the odd-number is set to be three or more. The auxiliary pattern is disposed on the fixed pitch and within the second device pattern and configured not to be resolved by light exposure.

Pattern layout for forming integrated circuit

A pattern creation method, including laying out data of a most extreme end pattern of integrated circuit patterns on a first layer and laying out data of the integrated circuit patterns excluding the most extreme end pattern on a second layer, extracting data of a first most proximate pattern being most proximate to the most extreme end pattern from the second layer and converting the extracted data to a third layer, generating data of a contacting pattern which contacts both the first most proximate pattern and the most extreme end pattern in a fourth layer, generating data of a non-overlapping pattern of the contacting pattern excluding overlapping portions with the most extreme end pattern and the first most proximate pattern in a fifth layer, extracting data of a second most proximate pattern being most proximate to the non-overlapping pattern and converting the extracted data to the first layer.

Pattern creation method, mask manufacturing method and semiconductor device manufacturing method

A photomask quality estimation system comprises a measuring unit, a latitude computation unit and an estimation unit. The measuring unit measures the mask characteristic of each of a plurality of chip patterns formed on a mask substrate. The latitude computation unit computes the exposure latitude of each chip pattern based on the mask characteristic. The estimation unit estimates the quality of each chip pattern based on the exposure latitude.

Photomask quality estimation system and method for use in manufacturing of semiconductor device, and method for manufacturing the semiconductor device

A mask pattern data generating method is disclosed, which comprises preparing mask pattern data which corresponds to a design pattern including a pair of line patterns formed of two line patterns, and disposing an auxiliary pattern which is un-transferable to a resist film at a center of a space region between the pair of line patterns, in which the disposing of the auxiliary pattern includes obtaining a shape of the auxiliary pattern which meets formulae in which a width in the short edge direction of the auxiliary pattern, a space width between the auxiliary pattern and one of the pair of line patterns, a wavelength of an exposure light emitted by a projection aligner using a photo mask at exposure, and a numerical apertures of a projection lens of the projection aligner are defined as parameters, and disposing the obtained auxiliary pattern at the center of the space region.

Mask pattern data generating method, photo mask manufacturing method, and semiconductor device manufacturing method

A temperature calibration method for a baking apparatus comprising forming a photoresist film onto a substrate, forming a latent image of a dose monitor mark onto the photoresist film, preparing baking processing apparatuses, baking the substrate or another substrate by temperature settings performed every repeat of a series of the forming the resist film and the forming the latent image with each prepared baking apparatus, cooling the baking-processed substrate, measuring a length of the latent image of the dose monitor mark after the cooling or a length of a dose monitor mark which being obtained by developing the resist film, determining relationship between a temperature setting and an effective dose in advance, and calibrating temperature settings corresponding to the each baking processing apparatus to be obtained a predetermined effective dose on the basis of the determining relationship and the measured length corresponding to the each baking processing apparatus.

Temperature calibration method for baking processing apparatus, adjustment method for development processing apparatus, and method of manufacturing semiconductor apparatus

There is disclosed a wafer flatness evaluation method includes measuring front and rear surface shapes of a wafer. The wafer front surface measured is divided into sites. Then, a flatness calculating method is selected according to a position of the site to be evaluated and flatness in the wafer surface is acquired.

Wafer flatness evaluation method, wafer flatness evaluation apparatus carrying out the evaluation method, wafer manufacturing method using the evaluation method, wafer quality assurance method using the evaluation method, semiconductor device manufacturing method using the evaluation method and semiconductor device manufacturing method using a wafer evaluated by the evaluation method

There is disclosed a mask pattern data forming method comprising arranging patterns with a minimum pitch in parallel or vertically in an X or Y direction, where directions diagonally connected with respect to respective centers of gravity of the double-pole or the quadrupole illumination are defined as the X and Y direction, classifying patterns or pattern groups with a pitch larger than the patterns with the minimum pitch into a pattern type with a pitch whose exposure margin is larger than that of the patterns with the minimum pitch and a pattern type with a pitch whose exposure margin is smaller than that of the patterns with the minimum pitch; and arranging patterns or pattern groups classified into the pattern type whose exposure margin is smaller than that of the patterns with the minimum pitch in a direction deflected by 45&#xb0; or 135&#xb0; from the patterns with the minimum pitch.

Mask pattern data forming method, photomask and method of manufacturing semiconductor device

A method of manufacturing a semiconductor device includes preparing a projection exposure apparatus and a photomask, the photomask having a transparent substrate and a light shield film arranged in patterns to be transferred to a resist film on a wafer. The patterns include a circuit mask pattern, and first and second mark mask patterns having dimensions which change in accordance with exposure of the resist film. The method further includes forming first and second exposure monitor marks by causing phasing differences of 180 degrees and zero degrees, respectively, of light passing through the corresponding first and second mark mask patterns; measuring the first and second exposure monitor marks; calculating first and second effective exposures based on measured dimensions of the first and second exposure monitor marks; comparing variations of the first and second effective exposures; and changing at least one of a deposit condition of a front-end film formed under the resist film or a resist film coating condition if a variation of the first effective exposure differs from a variation of the second effective exposure.

Exposure control method and method of manufacturing a semiconductor device

Growing community of inventors

Tokyo, Japan

Tadahito Fujisawa