Nec Corporation

Tohoku University

Nec Electronics Corporation

Japan Science and Technology Agency

Riken Corporation

Tadahiko Sugibayashi

Noboru Sakimura

Takeshi Honda

Ryusuke Nebashi

Isao Naritake

Yasuji Koshikawa

Takahiro Hara

Nobuyuki Ishiwata

Tetsuhiro Suzuki

Yukihide Tsuji

Hideo Ohno

Shunsuke Fukami

Norikazu Ohshima

Hideaki Numata

Satoshi Utsugi

Sadahiko Miura

Kaoru Mori

Tatsuya Matano

Makoto Miyamura

Takahiro Hanyu

Ayuka Tada

Masami Hanyu

Ryuji Yamamura

Koji Kawata

Tetsuo Endoh

Shoji Ikeda

Munehiro Tada

Kiyokazu Nagahara

Yuji Nakajima

Toshitsugu Sakamoto

Tsuyoshi Hasegawa

Hiroshi Takada

Atsushi Kamijo

Kenichi Shimura

Mamoru Fujita

Masakazu Aono

Hisao Kawaura

Hironobu Tanigawa

Toshio Takeshima

Eiji Kariyada

Kazuya Terabe

Tomonobu Nakayama

Kiyotaka Tsuji

Tatsunori Murotani

Tohru Mogami

Hisao Matsutera

Yoshiharu Aimoto

Hiroaki Honjou

Michihiko Yamanouchi

Shuichi Tahara

Shoun Matsunaga

In the cases of performing programming by forming a two-terminal-type variable resistance element on a semiconductor device, it has been difficult to control the programming, and malfunctions have often occurred. This switching element includes at least a first variable resistance element, a second variable resistance element, a first rectifying element, and a second rectifying element, one end of the first variable resistance element and one end of the second variable resistance element are respectively connected to one end of the first rectifying element and one end of the second rectifying element, and each of the rectifying elements has two terminals.

Switching element, semiconductor device, and semiconductor device manufacturing method

In order to provide a technique for reducing an area of a content addressable memory cell and suppressing a leak current in a content addressable memory which calculates similarity, a content addressable memory cell of the present invention, comprising: a resistance network which includes plural current paths, a logic circuit for selecting a current path in response to input data, and a variable-resistance-type non-volatile memory element that is arranged on at least one current path and stores data and whose resistance value is changed according to a result of logical calculation based on the input data and the stored data; and a charge/discharge circuit which is connected with the resistance network and a match line and whose delay time from inputting a signal through the match line until outputting the signal is changed according to the result of logical calculation based on the input data and the stored data.

Content addressable memory cell and content addressable memory

In order to provide a crossbar switch type memory circuit designed to be usable in normal circumstances even when a resistance change element is in an adverse state, the present invention is provided with: a first unit including a first column wiring to which one end of a first resistance change element is connected, a first power supply-side transistor for controlling the connection of the first column wiring and a power supply node, a first ground-side transistor, of a reverse operation type to the first power supply-side transistor, for controlling the connection of the first column wiring and a ground node, and a first polarity control line for causing the first power supply-side transistor or the first ground-side transistor to turn on and the other to turn off by a polar signal from a polar signal terminal, the first polarity control line being connected to the control terminals of the first power supply-side transistor and first ground-side transistor; a second unit including a second column wiring to which one end of a second resistance change element is connected, a second power supply-side transistor, of the same operation type as the first power supply-side transistor, for controlling the connection of the second column wiring and the power supply node, a second ground-side transistor, of a reverse operation type to the second power supply-side transistor, for controlling the connection of the second column wiring and the ground node, a logic inversion circuit for inverting the polarity of the polar signal from the polar signal terminal and outputting the polarity-inverted signal, and a second polarity control line for causing the second power supply-side transistor or the second ground-side transistor to turn on and the other to turn off by a polar signal from the logic inversion circuit, the second polarity control line being connected to the control terminals of the second power supply-side transistor and second ground-side transistor; and n row wirings (n: positive integer) to which the other ends of the first and second resistance change elements are connected.

Crossbar switch type memory circuit, look-up table circuit, and programming method

A semiconductor device includes a current control unit whose conductance is variable and a control unit configured to control the conductance of the current control unit. The current control unit is connected to a direct current power source in parallel with a load for the direct current power source, through a capacitor. The control unit sets the current control unit to a first conductance when the direct current power source and the load are not in a conduction state, and sets the current control unit to a second conductance larger than the first conductance when the direct current power source and the load are in the conduction state.

Semiconductor device, power supply control method of semiconductor device, and sensor node

A disclosed magnetic memory element includes: a magnetization free layer formed of a ferromagnetic substance having perpendicular magnetic anisotropy; a response layer provided so as to be opposed to the magnetization free layer and formed of a ferromagnetic substance having perpendicular magnetic anisotropy; a non-magnetic layer provided so as to be opposed to the response layer on a side opposite to the magnetization free layer and formed of a non-magnetic substance; and a reference layer provided so as to be opposed to the non-magnetic layer on a side opposite to the response layer and formed of a ferromagnetic substance having perpendicular magnetic anisotropy. The magnetization free layer includes a first magnetization fixed region and a second magnetization fixed region which have magnetization fixed in directions antiparallel to each other, and a magnetization free region in which a magnetization direction is variable.

Magnetic memory element and magnetic memory

A nonvolatile logic gate device is configured to include a resistive network of a memory structure in which at least three nonvolatile resistive elements are connected, a reference resistive network as a reference resistance providing a tolerance of the memory structure to a resistance value of the resistive network of the memory structure, a writing part operable to selectively write or rewrite a value of each of the nonvolatile resistive elements in the resistive network into a maximum or a minimum corresponding to a logical value to be read when data are stored into the resistive network, and a logic circuit structure operable to use, as a logical value of the memory structure, a value obtained by comparison between the resistance value of the resistive network and the resistance value of the reference resistive network.

Nonvolatile logic gate device

Provided is a magnetic domain wall displacement memory cell, including a recording layer including a magnetic film, the recording layer including: a magnetization reversal region in which magnetization is reversible; and first and second magnetization fixed regions that supply a spin-polarized electron to the magnetization reversal region. The magnetic domain wall displacement memory cell is configured so that a first region in which magnetization reversal occurs due to a first current flowing in a direction parallel to a film surface of the recording layer and a first magnetic field component in the direction parallel to the film surface of the recording layer is formed, and a second region in which no magnetization reversal occurs is formed.

Magnetic-domain-wall-displacement memory cell and initializing method therefor

A magnetoresistive effect element of the present invention includes: a domain wall motion layer, a spacer layer and a reference layer. The domain wall motion layer is made of ferromagnetic material with perpendicular magnetic anisotropy. The spacer layer is formed on the domain wall motion layer and made of non-magnetic material. The reference layer is formed on the spacer layer and made of ferromagnetic material, magnetization of the reference layer being fixed. The domain wall motion layer includes at least one domain wall, and stores data corresponding to a position of the domain wall. An anisotropy magnetic field of the domain wall motion layer is larger than a value in which the domain wall motion layer can hold the perpendicular magnetic anisotropy, and smaller than an essential value of an anisotropy magnetic field of the ferromagnetic material of the domain wall motion layer.

Magnetoresistive effect element and magnetic random access memory using the same

Provided is a nonvolatile content addressable memory. Each word circuit includes a plurality of segments having an order relation. Each of the segments includes one or more memory cells. Each of the memory cells includes a nonvolatile storage element. Each of the segments includes a power switch for turning on/off a power of a memory cell of the segment. During stand-by, all the power switches are turned off, and, in search operation, the power switch is turned on as necessary for each of the segments.

Nonvolatile content addressable memory and method for operating same

Provided is a nonvolatile resistor network assembly characterized by that: it comprises a first and a second resistor network which are each composed of a plurality of nonvolatile resistive elements connected together; it also comprises a write means for writing into the first and second resistor networks; and writing into the first and second resistor networks is performed by the use of the write means in a manner to make total resistances of respectively the first and second resistor networks different from each other. Further provided is a nonvolatile logic gate which performs logical operation using stored data determined by the total resistances of the respective nonvolatile resistor networks.

Nonvolatile resistor network assembly and nonvolatile logic gate with increased fault tolerance using the same

A magnetoresistive elementhaving a memory cellaccording to the present invention contains a first lower terminal nand a second lower terminal nrespectively connected to both ends of a conductive layerwhose longitudinal direction is different from the column direction (X direction). Further, the gates of the first transistors Mrespectively included in two memory cells among the plurality of memory cellsand adjacent to each other in a row direction (Y direction) are commonly connected to a first word line. As a result, without increase of the cell area, it becomes possible to reserve a margin in the dimension of the cell structure or in the process for MRMA.

Semiconductor storage device and its manufacturing method

A magnetic memory cellis provided with a magnetic recording layerwhich is a ferromagnetic layer and a pinned layerconnected with the magnetic recording layerthrough a non-magnetic layer. The magnetic recording layerhas a magnetization inversion region, a first magnetization fixed regionand a second magnetization fixed region. The magnetization inversion regionhas a magnetization whose orientation is invertible and overlaps the pinned layer. The first magnetization fixed regionis connected with a first boundary Bin the magnetization inversion regionand a magnetization orientation is fixed on a first direction. The second magnetization fixed regionis connected with a second boundary Bin magnetization inversion regionand a magnetization orientation is fixed on a second direction. The first direction and the second direction are opposite to each other.

Magnetic memory cell and magnetic random access memory

An MRAM of a spin transfer type is provided with a memory celland a word driver. The memory cellhas a magnetic resistance elementand a selection transistor TR having one of source/drain electrodes which is connected with one end of the magnetic resistance element. The word driverdrives a word line WL connected with a gate electrode of the selection transistor TR. The word driverchanges a drive voltage of the word line WL according to the write data DW to be written in the magnetic resistance element

MRAM having variable word line drive potential

Provided is an operation method which can be applied to a PRAM, an ReRAM, and a solid electrolyte memory which stores error correction codes, each of which comprises of symbols, each of which comprises bits, and which codes allow error correction in units of symbols. In the operation method, the respective symbols are read by using different reference cells. When a correctable error is detected in read data from data cells forming the error correction codes and corresponding to an input address, a data in a data cell corresponding to the error bit is corrected for a first error symbol of an one bit error pattern, and data in a reference cell that is used to read the second error symbol are corrected for a second error symbol related to a multi-bit error pattern.

Semiconductor storage device and method of operating the same

A non-volatile logic circuit includes an input section, a control section and an output section. The input section has perpendicular magnetic anisotropy and has a ferromagnetic layer whose magnetization state is changeable. The control section includes a ferromagnetic layer. The output section is provided in a neighborhood of the input section and the control section and includes a magnetic tunnel junction element whose magnetization state is changeable. The magnetization state of the input section is changed based on the magnetization state. A magnetization state of the magnetic tunnel junction element of the output section which state is changed based on the magnetization state of the ferromagnetic material of the control section and the magnetization state of the ferromagnetic material of the input section.

Non-volatile logic circuit

Growing community of inventors

Tokyo, Japan

Tadahiko Sugibayashi