Nec Corporation

Nscore, Inc.

Tadahiko Horiuchi

Takashi Ishigami

Hiroshi Ito

Shinya Ito

Yoshihisa Matsubara

Noriaki Oda

Akira Matsumoto

Toru Tatsumi

Kazuhiko Endo

Ko Noguchi

Masahiko Nakamae

Yoshishige Matsumoto

Hiroyuki Nakamura

Naohiko Kimizuka

Hitoshi Wakabayashi

Koichiro Okumura

Tohru Mogami

Kenji Noda

Kazuhiko Oyama

Takemitsu Kunio

A semiconductor memory device includes a bit line pairs, a source line, a word line, and a memory cell array including a plurality of memory cells arranged in a row and column directions, wherein the memory cell is a pair of p-type transistors formed on an n-type well, wherein one of terminals of the transistor is a Schottky barrier junction consisting of a metal thin film formed on the n-type well, and the other terminal is connected to the source line.

Semiconductor memory device

It is provided a circuit for generating finger print code data comprising: plural pairs of first transistors, each of the first transistors having a source formed in the substrate, a drain formed in the substrate, a channel formed in the substrate between the source and the drain, a gate insulating layer formed on the channel, a gate electrode formed over the gate insulating layer, and an insulating sidewall formed at a side surface of the gate electrode; plural pairs of cross coupled second transistors, each of the plural pairs of cross coupled second transistors having drains and commonly connected sources, corresponding to each of the plural pairs of first transistors; and plural pairs of third transistors, each of the plural pairs of third transistors corresponding to each of the plural pairs of cross coupled second transistors.

Secure fingerprint data generating device

A nonvolatile memory cell includes a first-conductivity-type silicon substrate, a metal layer formed in a surface of the first-conductivity-type silicon substrate, a second-conductivity-type diffusion layer formed in the surface of the first-conductivity-type silicon substrate and spaced apart from the metal layer, an insulating film disposed on the surface of the first-conductivity-type silicon substrate between the metal layer and the second-conductivity-type diffusion layer, a gate electrode disposed on the insulating film between the metal layer and the second-conductivity-type diffusion layer, and a sidewall disposed at a same side of the gate electrode as the metal layer and situated between the gate electrode and the metal layer, the sidewall being made of insulating material.

Nonvolatile memory cell employing hot carrier effect for data storage

Nonvolatile memory device

A nonvolatile memory device includes a word line, four or more bit lines, three or more MIS transistors having gate nodes thereof connected to the word line, the N-th (N: positive integer) one of the MIS transistors having two source/drain nodes thereof connected to the N-th and N+1-th ones of the bit lines, respectively, a sense circuit having two nodes and configured to amplify a difference between potentials of the two nodes, and a switch circuit configured to electrically couple the N-th and N+2-th ones of the bit lines to the two nodes of the sense circuit, respectively, and to electrically couple the N+1-th one of the bit lines to a fixed potential, for any numerical number N selected to detect single-bit data stored in the N-th and N+1-th ones of the MIS transistors.

A nonvolatile semiconductor memory device includes an MIS transistor having nodes, a control circuit configured to apply a first set of potentials to the nodes to cause an irreversible change in transistor characteristics, to apply a second set of potentials to the nodes to cause a first current to flow through the MIS transistor in a first direction, and to apply the second set of potentials to the nodes to cause a second current to flow through the MIS transistor in a second direction opposite the first direction, and a sense circuit configured to produce a signal responsive to a difference between the first current and the second current.

Nonvolatile semiconductor memory device using MIS transistor

A memory circuit includes a latch having a first node and a second node to store data such that a logic level of the first node is an inverse of a logic level of the second node, a MIS transistor having a gate node, a first source/drain node, and a second source/drain node, the first source/drain node coupled to the first node of the latch, and a control circuit configured to control the gate node and second source/drain node of the MIS transistor in a first operation such that a lingering change is created in transistor characteristics of the MIS transistor in response to the data stored in the latch, wherein the MIS transistor includes a highly-doped substrate layer, a lightly-doped substrate layer disposed on the highly-doped substrate layer, diffusion regions formed in the lightly-doped substrate layer, a gate electrode, sidewalls, and an insulating film.

Nonvolatile semiconductor memory circuit utilizing a MIS transistor as a memory cell

A memory circuit includes a latch having a first node and a second node, a MIS transistor having a gate node, a first source/drain node coupled to the first node of the latch, and a second source/drain node, and a control circuit configured to control the gate node and second source/drain node to make a lingering change in a threshold voltage of the MIS transistor in a first operation and to cause the latch in a second operation to store data responsive to whether a lingering change in the threshold voltage is present, wherein the MIS transistor includes diffusion regions, a gate electrode, and sidewalls, wherein a metallurgical junction of each of the diffusion regions is positioned under the gate electrode, and a lateral boundary of a depletion layer in the diffusion region serving as a drain is positioned under a corresponding one of the sidewalls in the first operation.

Mis-transistor-based nonvolatile memory circuit with stable and enhanced performance

A memory circuit includes a latch having a first node and a second node to store data such that a logic level of the first node is an inverse of a logic level of the second node, a MIS transistor having a gate node, a first source/drain node, and a second source/drain node, the first source/drain node coupled to the first node of the latch, and a control circuit configured to control the gate node and second source/drain node of the MIS transistor to make an upward lingering change in a threshold voltage of the MIS transistor in a first operation in response to data stored in the latch and to make a downward lingering change in the threshold voltage in a second operation in response to data stored in the latch.

MIS-transistor-based nonvolatile memory for multilevel data storage

A nonvolatile memory circuit includes a flip-flop to degrade an internal circuit irreversibly based on a voltage applied to a first or second bit line so as to latch data in a nonvolatile manner, a first switch coupled between a first output terminal of the flip-flop and the first bit line, a second switch coupled between the first output terminal of the flip-flop and the first bit line, a third switch coupled between a second output terminal of the flip-flop outputting an inverse of an output of the first output terminal and the second bit line, and a fourth switch coupled between the second output terminal of the flip-flop and the second bit line.

Nonvolatile memory circuit

A memory circuit includes a latch having a first node and a second node, a plate line, a word selecting line, a first MIS transistor having source/drain nodes thereof coupled to the first node and the plate line, respectively, and a gate node thereof coupled to the word selecting line, a second MIS transistor having source/drain nodes thereof coupled to the second node and the plate line, respectively, and a gate node thereof coupled to the word selecting line, and a driver configured to set the plate line to a first potential causing a current to flow in a first direction through the first MIS transistor in a first operation mode and to a second potential causing a current to flow in a second direction through the first MIS transistor in a second operation mode, the first operation mode causing a lingering change in characteristics of the first MIS transistor.

Nonvolatile memory circuit based on change in MIS transistor characteristics

A memory circuit includes a latch having a first node and a second node, a word selecting line, a first MIS transistor having the source/drain nodes thereof coupled to the first node and a predetermined node, respectively, and the gate node thereof coupled to the word selecting line, a second MIS transistor having the source/drain nodes thereof coupled to the second node and the predetermined node, respectively, and the gate node thereof coupled to the word selecting line, and a control circuit configured to subject in a write mode, one of the first MIS transistor and the second MIS transistor to bias conditions that cause a lingering change in transistor characteristics thereof, and to subject in a recovery mode both the first MIS transistor and the second MIS transistor for equal amount of time to equal bias conditions that cause a lingering change in transistor characteristics thereof.

Storage and recovery of data based on change in MIS transistor characteristics

A structure and manufacturing process of a low dielectric constant interlayer insulating film used between wiring layers and semiconductor devices using such film are disclosed. The insulating film which can withstand in an actual process comprises an amorphous carbon fluoride film. A diamond like carbon film and a silicon excess layer are disposed on both sides of the amorphous carbon fluoride film to be inserted between the wiring layers, whereby adhesion to wiring and another insulating film contacting it is significantly enhanced. In addition, a silicon based insulating film is disposed and flattened on a multilayer film containing an amorphous carbon fluoride film buried with a wiring layer, and is used as a hard mask for anisotropically etching the diamond like carbon film and the amorphous carbon fluoride film with oxygen plasma to form a via hole.

Insulating film comprising amorphous carbon fluoride, a semiconductor device comprising such an insulating film, and a method for manufacturing the semiconductor device

Disclosed is a method for making a MIS transistor that a gate electrode and gate insulating film are formed on a semiconductor substrate with a channel region formed implanting an impurity of one conductivity type thereinto, which has the steps of: implanting hydrogen ions through said gate electrode and gate insulating film into said channel region under said gate electrode; ion-implanting an impurity of a conductivity type reverse to said one conductivity type self-aligned to said gate electrode to form a source/drain region; and conducting thermal treatment in an inert atmosphere or nitrogen atmosphere.

Method for making MIS transistor

A semiconductor device of the present invention is a semiconductor device of a complementary MIS field effect transistor, wherein an anode of a first diode is connected to a silicon substrate of a first conduction type while a cathode of the first diode is connected to a first power supply while a cathode of a second diode is connected to a well of the other conduction type and an anode of the second diode is connected to a second power supply.

Growing community of inventors

Isehara, Japan

Tadahiko Horiuchi