Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Corporation

Ryoden Semiconductor System Engineering Corporation

Tadaharu Minato

Katsumi Nakamura

Masana Harada

Tetsuo Takahashi

Tetsuya Nitta

Katsuomi Shiozawa

Shuuichi Tominaga

Hideki Takahashi

Kazutoyo Takano

Hidenori Nishihara

Shigenobu Maeda

Toshiaki Iwamatsu

Takashi Ipposhi

Yasuo Inoue

Hideki Nakamura

Tatsuya Kunikiyo

Kazuyuki Sugahara

Akio Uenishi

Shinji Aono

Takahiro Nakatani

Yusuke Kawase

Hisayuki Nishimura

Katsumi Uryu

Kazunori Kanada

Mikio Ikeda

Junji Tateishi

Hidekazu Yamamoto

Mitsuru Kaneda

Kenichi Ootsuka

Norifumi Tokuda

Tetsuya Takami

Junichi Murakami

Shuuichi Tominga

Akio Uenisi

A SEB resistance evaluation method includes: disposing an excitation source within a model of a semiconductor device; and determining an energy of the excitation source at which the semiconductor device exhibits thermal runaway, while varying a voltage applied to the model of the semiconductor device and the energy of the excitation source.

SEB resistance evaluation method and SEB resistance evaluation device

The object is to provide a technique for adjusting a turn-on operation and a turn-off operation of a transistor independently from each other in simulation for evaluating characteristics of the transistor. A simulation circuit for simulation for evaluating characteristics of a transistor includes a gate power supply configured to apply a voltage to a gate terminal of the transistor, a first diode connected between the gate terminal and the gate power supply, and a second diode connected in antiparallel with the first diode.

Simulation circuit and simulation method

A laser annealing device of the present invention includes a stage on which a heating object is placed, a first laser element which emits first continuous laser light, a first optical system which leads the first continuous laser light to the heating object to form a first application region on the heating object, a second laser element which emits second continuous laser light having a wavelength shorter than that of the first continuous laser light, a second optical system which leads the second continuous laser light to the heating object to form a second application region on the heating object, and a system controller which executes scanning with the first application region and the second application region so that each portion of the heating object is scanned with at least part of the first application region before being scanned with the second application region.

Laser annealing device with multiple lasers

According to the present invention, since the buffer layer is formed by multiple ion implantations of different acceleration energies and the non-diffusion region in which impurity do not diffuse is left between the buffer layer and the collector layer, the semiconductor device which can supply sufficient holes to the drift layer at the turn-off can be manufactured while the withstand voltage is ensured.

Semiconductor device manufacturing method

An object of the present invention is to provide a trench gate type IGBT achieving both retention of withstand voltage and lowering of ON-state voltage and to provide a method for manufacturing the trench gate type IGBT. The IGBT according to the present invention is an SJ-RC-IGBT which includes a drift layer having super junction structure, and includes an IGBT area and an FWD area on the rear surface. In the IGBT according to the present invention, a first drift layer has an impurity concentration of 1&#xd7;10atms/cmor higher and lower than 2&#xd7;10atms/cm, and a thickness of 10 &#x3bc;m or larger and smaller than 50 &#x3bc;m; and that a buffer layer has an impurity concentration of 1&#xd7;10atms/cmor higher and lower than 2&#xd7;10atms/cm, and a thickness of 2 &#x3bc;m or larger and smaller than 15 &#x3bc;m.

Insulating gate-type bipolar transistor

A trench gate IGBT designed to reduce on-state voltage while maintaining the withstand voltage, including a first drift layer formed on a first main surface of a buffer layer, a second drift layer of the first conductivity type formed on said first drift layer, a base layer of a second conductivity type formed on the second drift layer, an emitter layer of the first conductivity type selectively formed in the surface of the base layer, and a gate electrode buried from the surface of the emitter layer through into the second drift layer with a gate insulating film therebetween, wherein said first drift layer has a structure in which a first layer of the first conductivity type and a second layer of the second conductivity type are repeated in a horizontal direction.

Insulated gate bipolar transistor and manufacturing method thereof

A method for manufacturing a semiconductor device includes the steps of forming a P-type region on a surface of a semiconductor substrate, forming at least one Al electrode on the P-type region, forming an interlayer film in contact with the at least one Al electrode, the interlayer film being of a material which is less reactive with Si than is Al, and forming a semi-insulating film on the interlayer film, the semi-insulating film containing Si.

Method for manufacturing semiconductor device

A device and a device manufacturing process. First, a gettering layer is formed on the bottom surface of a silicon substrate. Gates having a MOS structure are then formed on the principal surface of the silicon substrate, and the gettering layer is removed. According to this manufacturing method, the formation of the gates having a MOS structure is performed such that the gettering layer getters dissolved oxygen present in the silicon substrate. This reduces the concentration of dissolved oxygen in the silicon substrate, resulting in improved device characteristics.

Semiconductor device including a gettering layer and manufacturing method therefor

A semiconductor substrate has a trench in a first main surface. An insulated gate field effect part includes a gate electrode formed in the first main surface. A potential fixing electrode fills the trench and has an expanding part expanding on the first main surface so that a width thereof is larger than the width of the trench. An emitter electrode is formed on the first main surface and insulated from the gate electrode electrically and connected to a whole upper surface of the expanding part of the potential fixing electrode. Thus, a semiconductor device capable of enhancing reliability in order to prevent an aluminum spike from generating and a manufacturing method thereof can be provided.

Semiconductor device and manufacturing method thereof

In a MOSFET using SiC a p-type channel is formed by epitaxial growth, so that the depletion layer produced in the p-type region right under the channel is reduced, even when the device is formed in a self-aligned manner. Thus, a high breakdown voltage is obtained. Also, since the device is formed in a self-aligned manner, the device size can be reduced so that an increased number of devices can be fabricated in a certain area and the on-state resistance can be reduced.

Power semiconductor device having raised channel and manufacturing method thereof

A pin diode is formed by a pcollector region, an n type buffer region, an nregion and an ncathode region. A trench is formed from the surface of ncathode region through ncathode region to reach nregion. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of ncathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to ncathode region. An anode electrode is formed to be electrically connected to pcollector region. The ncathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.

A semiconductor device of the present invention has a pn-repeating structure that a structure in which a p-type impurity region () and an n-type drift region () are aligned side by side is repeated twice or more, and a low concentration region which is either p-type impurity region () or n-type drift region () located at the outermost portion of this pn-repeating structure has the lowest impurity concentration or has the least generally effective charge amount among all the p-type impurity regions () and n-type drift regions () forming the pn-repeating structure. Thereby, the main withstand voltage of a power semiconductor device to which a three dimensional multi-RESURF principle is applied, wherein the element withstand voltage is specifically in the broad range of 20 to 6000 V, can be improved and the trade-off relationship between the main withstand voltage and the ON resistance can also be improved, so that an inexpensive semiconductor device of which the power loss is small and of which the size of the chip is small can be obtained. In addition, a trench of a dotted line trench (DLT) structure and a manufacturing method corresponding to this can be used, so that a semiconductor device with a good yield can be obtained at low cost.

Semiconductor device and manufacturing method for the same

A semiconductor device that includes an insulating substrate, a plurality of semiconductor layers arranged to be isolated from one another on the insulating substrate, and a semiconductor element independently provided on the semiconductor layers. Further, a trench may extend from the main surface to the substrate and have an inner wall covered with an insulating film. At least one of an edge on the side of the substrate and an edge on the side opposite thereof of the semiconductor layer has a rounded surface. Further, an angle between a line tangent to a surface having a smallest radius of curvature of the rounded surface of the edge and the main surface ranges from 30&#xb0; to 60&#xb0; at a section of the edge.

Semiconductor device including trench with at least one of an edge of an opening and a bottom surface being round

A semiconductor device includes an n-type semiconductor substrate () including a p-type collector layer () formed in a second main surface side thereof, a trench () is formed in a peripheral portion of the semiconductor substrate () so as to surround the inside and reach the collector layer () from a first main surface of the semiconductor substrate (), and a p-type isolation region () formed by diffusion from a sidewall of the trench () is provided to be connected to the collector layer (). The trench () is filled with a filling material ().

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Tokyo, Japan

Tadaharu Minato