Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Matsushita Electronics Corporation

Tadaaki Mimura

Masao Takahashi

Toshihiko Sakashita

Hiroaki Fujimoto

Takayuki Yoshida

Koji Takemura

Ichiro Yamane

Yoshiaki Kasuga

Takio Yamashita

Toshio Matsuki

Shin Hashimoto

Takashi Otsuka

Toshiyuki Fukuda

Yoshirou Nakata

Tsuyoshi Hamatani

Kenji Ueda

Atuhito Mizutani

Electrode pads respectively have a probe region permitting probe contact and a non-probe region. In each of the electrode pads arranged zigzag in two or more rows, a lead interconnect for connecting another electrode pad with an internal circuit is not placed directly under the probe region but placed directly under the non-probe region.

Semiconductor device

A semiconductor device comprises a first insulating film formed on a semiconductor substrate, a first metal pattern formed on the first insulating film, a second insulating film formed on the first metal pattern, a second metal pattern formed on the second insulating film, and a third metal pattern formed in the second insulating film and connecting between the first metal pattern and the second metal pattern. The third metal pattern is a single continuous structure, and the principal orientation axes of crystals of a metal constituting the third metal pattern are parallel to the principal surface of the semiconductor substrate.

Semiconductor device with multilayered metal pattern

A pad section serving as an electrode for external connection of a semiconductor device includes a first pad metal () formed in the top layer, a second pad metal () formed under the first pad metal () via an interlayer insulating film (), and vias () which penetrate the interlayer insulating film () and electrically connect the first pad metal () and the second pad metal (). The first pad metal () and the second pad metal () have edges displaced from each other so as not to be aligned with each other along the thickness direction of each layer. Thus, it is possible to reduce stress occurring on an edge of the second pad metal (), thereby reducing damage on the interlayer insulating film () and so on.

Electrode pad section for external connection

Circuits under electrode terminals and a nonconductor layer of the electrode terminals in semiconductor devices are prevented from being damaged during a test, such as a burn-in test, on the semiconductor devices formed on a wafer. Alignment patterns provided on the semiconductor wafer have detector electrode terminals and conductor electrode terminals. A detector electrode terminal surrounds a conductor electrode terminal separated by a gap from the detector electrode terminals and a portion of the surrounding detector electrode terminal is open.

Semiconductor wafer and testing method therefor

The present invention reduces crosstalk, which occurs as a result of interference between signals running in each of respective wiring layers of a first semiconductor chip and a second semiconductor chip stacked surface to surface with a small gap. The semiconductor device includes a first semiconductor chip 1 having a first electrode pad 2 and a first wiring layer 9 in the main surface, and a second semiconductor chip 5 having a second electrode pad 6 and a second wiring layer 10 in the main surface confronting the first semiconductor chip. A bump 4 is provided for electrically coupling the first electrode pad 2 and the second electrode pad 6 together. An insulation layer 8 is disposed between the main surfaces of first semiconductor chip 1 and second semiconductor chip 5. An electro-conductive layer 7 is disposed between the main confronting surfaces of the first semiconductor chip and the second semiconductor chip.

Structure of chip on chip mounting preventing from crosstalk noise

A microcomputer chip is formed with a CPU core, a peripheral circuit, a built-in ROM, and a built-in RAM. An emulation functional chip is formed with an emulation control circuit for controlling the whole process of emulation. First electrode pads formed on the functional surface of the microcomputer chip are electrically interconnected to second electrode pads formed on the functional surface of the emulation functional chip with connecting bumps interposed therebetween. The microcomputer chip and the emulation functional chip are modularized using an insulating resin with the first electrode pads being connected to the second electrode pads.

The present invention reduces crosstalk noise, which occurs as a result of interference between signals running in each of respective wiring layers of a first semiconductor chip and a second semiconductor chip stacked surface to surface with a small gap. The semiconductor device includes a first semiconductor chip (1) having a first electrode pad (2) and a first wiring layer (9), and a second semiconductor chip (5) having a second electrode pad (6) and a second wiring layer (10). A bump (4) is provided for electrically coupling the first electrode pad (2) and the second electrode pad (6). An insulation layer 8 is disposed between confronting surfaces of the first semiconductor chip (1) and the second semiconductor chip (5). An electro-conductive layer (7) is disposed between the confronting surfaces of the first semiconductor chip and the second semiconductor chip.

Growing community of inventors

Osaka, Japan

Tadaaki Mimura