Hitachi, Ltd.

Hitachi Ulsi Engineering Corp.

Hitachi Computer Engineering Co., Ltd.

501 Hitachi, Ltd.

Tadaaki Isobe

Teruo Tanaka

Katsuyoshi Kitai

Yasuhiro Inagami

Yoshiko Tamaki

Tadayuki Sakakibara

Bunichi Fujita

Shigeko Yazawa

Shigeko Hashimoto

Noboru Masuda

Naonobu Sukegawa

Shigeo Takeuchi

Masamori Kashiyama

Masakazu Yamamoto

Kazunori Nakajima

Toshimitsu Ando

Yoshiko Yasuda

Takayuki Nakagawa

Tatsuo Higuchi

Hiroaki Fujii

Hideya Akashi

Junji Nakagoshi

Masao Furukawa

Yuji Saeki

Tsuguo Matsuura

Masato Ishii

Tatsuru Toba

Masanao Ito

Masakazu Fukagawa

Toshiko Isobe

Toshihiro Yamagishi

Yuko Ishibashi

Yasuhiro Teramoto

Miki Miyaki

Mihoko Hashiba

Osamu Arakawa

Toshimitsu Andoh

Kohki Uwano

Tatsuya Ichiki

Makoto Koga

In a memory device capable of processing a small amount of data in a high speed, this memory device is suitable for various sorts of systems in which a plurality of access requests for continuous addresses are mixed with each other, and are issued as irregular requests to a memory subsystem. A data array is provided in a memory device having a memory cell. This data array may be arranged as a virtual register array having an arbitrary number of arbitrary word length. The data register array is accessed by employing a virtual register number and a virtual word number, which are supplied from an external circuit provided outside the memory device. In the memory device, both the virtual register number and the virtual word number, which are supplied from the external circuit, are converted into both an absolute register number and an absolute word number by an internally-provided converting circuit so as to access the data register array. With employment of such an arrangement, the respective structures of the data register array are separately optimized with respect to different application programs, so that accessing efficiencies can be improved.

Memory device for constituting a memory subsystem of a data processing apparatus

A memory system for use in a high-speed computer system, such as a super computer, has synchronous-type storage elements organized in groups for storing data. A storage control section has a clock generator circuit that generates parallel transfer clock signals that compensate for overall transfer delay when data is transferred to the storage elements. Each of the storage elements groups has a phase-locked locked loop circuit that outputs timing signals for accepting data, including address and control signals, etc., at the storage elements. Data is read out from the storage elements to a return data holding circuit of the storage control section using return parallel transfer clock signals, which are controlled by a control section phase-locked loop circuit that receives as an input a timing output of the phase-locked loop circuit of one of the storage element groups. A clock distribution circuit controls the supply of clock signals to a flip-flop group in the return data holding circuit. A timing signal supplied to one of the flip-flop circuits is returned to the storage control phase-locked loop circuit for controlling the timing of the acceptance of the transferred data in the flip-flop group of the return data holding circuit.

Storage apparatus

In an information processing system, a main storage access request issued from a processor is input to an access buffer mechanism provided in a memory control device, and sent via an operation request issue control mechanism to a main storage device constituted of a plurality of memory units (banks). In the memory control device, the operation status of each bank constituting the main storage device is managed and the number of banks under operation is counted. The predetermined number (operation bank limit number) of banks required to operate at a minimum is compared with the number (operation bank number) of banks under operation. If the operation bank number is smaller than the operation bank limit number, the memory control device instructs a dummy operation request generation mechanism to generate a dummy operation request, in order to prevent a large change in a power supply current to be caused by an abrupt change in the number of access requests to the main storage device and to realize a system stable operation. A dummy operation request generation mechanism determines a bank which executes a dummy operation, and an operation request issue control mechanism issues a dummy operation request to the determined bank in the main storage device.

Information processing system

Each of processors in a multiprocessor system has a circuit for sending a synchronizing signal to a storage controller (SC) connected thereto when executing a synchronization instruction such as a start, end or barrier synchronization instruction. Each of the SCs has a circuit for notifying the corresponding processor of establishment of a synchronization upon detection of completion of a check to be made by an address management table FAA and of the issuing of necessary cache cancel requests corresponding to a store instruction issued before the synchronization instruction and upon recognition of the fact that all the processors have sent their synchronizing signals and that the issuing of all the cache cancel requests have been complete.

Parallel processor synchronization and coherency control method and system

An instruction processor is employed which performs a cache coherence control according to a request from the storage controller. The storage controller is provided with a cache coherence control processing circuit, which performs the cache coherence control for the addresses which are the destinations of main memory accesses occurring with a data transfer. At the same time, the cache coherence control processing circuit performs the cache coherence control processing once for each cache line in the process of data transfer. The cache coherence control processing performed by software in connection with data transfer is obviated, improving the data transfer efficiency including the cache memory control and reducing limitations on program.

Message passing distributed shared memory system that eliminates

Data transmission apparatus and method

An information processing system is connected to a common storage and executes programs by use of processors. This system includes a common storage; a plurality of processors, connected to the common storage. Each processor executes an instruction to store data from common storage, and an instruction to load data from the common storage into the cache storage, wherein each processor includes a communication controller for, when detecting synchronization completion information for attaining synchronization of execution of instructions among a plurality of processors, sending synchronization completion information and receiving synchronization information from another processor; an instruction executing section for detecting a specified change of the flag of a specified location in the common storage by executing a Monitor instruction included in a program in response to synchronization information from the communication controller; an execution controller to execute subsequent instructions after the Monitor instruction, exclusive of a Load instruction to load data into a cache storage, until a change of the flag is detected by the execution section, wherein the processor allows instruction for loading data from common storage into the cache storage to be executed after the flag detection, and wherein the execution controller may include an inhibit resetting circuit to issue an inhibit instruction control signal to terminate the instruction send-out inhibiting action of the instruction inhibit circuit according to input from a service processor.

Processing instructions up to load instruction after executing sync flag

In a multiprocessor computer system, individual vector processors are provided with priority switching signal control circuits, respectively, and a storage control unit incorporating a priority control circuit. Priority bit information is provided for priority circuits incorporated in the storage control unit. Paths for priority switching signal issued in accordance with a number of requests as generated and types of instruction generating the requests are provided between the priority switching signal control circuits and the priority control circuit of the storage control unit, while paths for the priority switching signal as generated are provided between the priority control circuit and all the priority circuits.

Priority control with concurrent switching of priorities of vector

In transmitting and receiving signals between a plurality of units in a information processing system, signals can be transmitted and received between circuits operated by asynchronous clocks which are the same in period (frequency) but not necessarily to be the same in phase, thereby permitting the information processing system to operate with a shorter clock period. A delay circuit arranged in the communication path is so controllable that the data sent out in synchronism with the clock signal of a transmitting unit is correctly retrieved in synchronism with the clock signal of a receiving unit. Further, data having a predetermined simple pattern is sent out in synchronism with the clock signal of the transmitting unit, and it is decided whether the data has been correctly received by the receiving unit. The delay circuit is automatically controlled by use of the result of decision.

Data-transmitter-receiver

In a parallel processor system comprising a plurality of processor elements constituting a network, a source processor element wishing to broadcast data to a plurality of destination processor elements sends a broadcast request message containing the target data to a broadcast exchanger. The broadcast exchanger converts the received message into a broadcast message and sends it over the network to the destinations. A plurality of broadcast request messages, if transmitted parallelly to the broadcast exchanger, are serialized thereby so that only one broadcast message will be transmitted at a time over the network. This prevents deadlock from occurring between different broadcast messages. The routes for transmitting broadcast request messages and those for transmitting broadcast messages are arranged so as not to overlap with one another. This suppresses deadlock between any broadcast request message and broadcast message. The broadcast exchanger is replaced alternatively with one of the partial networks. These schemes all apply where long messages are transmitted through worm-hole routing.

Parallel processor system with a broadcast message serializing circuit

A parallel computer system includes a plurality of processor units, a data transfer network for interconnecting the processor units, a synchronizing network for allowing program execution to be performed synchronously by the individual processor units, a connecting unit for connecting the individual processor units and the synchronizing network, and an input unit connected to the synchronizing network. The connecting unit connects selectively the individual processor units to the synchronizing network in accordance with information inputted via the input unit. With the parallel computer system, a program can be executed synchronously in parallel by using a desired number of processor units of those incorporated in the system, whereby availability of processor resources of the system can be enhanced.

Parallel computer system

Data transmitter-receiver

Interprocessor priority control system for multivector processor

When a processor generates an access request to a plurality of continuous addresses to an RAM through a memory control apparatus, in order to enable a high speed process, a register which holds an address for accessing a memory cell and a register which holds an address for accessing a data buffer are separately provided in an RAM having memory cells and a plurality of row correspondence data buffers of the memory cells. A signal line to instruct the presence or absence of the use of the data buffer is provided between the processor and the memory control apparatus. The memory cell and the data buffer are accessed in parallel, thereby realizing a high processing speed. The processor designates so as to preferentially use the data buffer for an RAM access having an address continuity, thereby enabling the data to be accessed at a high speed.

Memory device having a plurality of sets of data buffers

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Hadano, Japan

Tadaaki Isobe