Altera Corporation

Tad Kwasniewski

Shoujun Wang

Haitao Mei

Bill W Bereza

Mashkoor Baig

William W Bereza

Rakesh H Patel

Jingcheng Zhuang

Qingjin Du

Yuming Tao

Farhad Zarkeshvari

Sergey Yuryevich Shumarayev

Charles E Berndt

Miao Li

Muhammad Usama

Charge pump circuitry is provided that is insensitive to charge sharing and current mismatch effects. The charge pump circuitry has an output node at which a charge pump output voltage is provided. A first current source charges the output node to increase the output voltage or a second current source discharge the output node to decrease the output voltage. The charge pump circuitry uses a unit-gain op-amp circuit to prevent charge sharing effects from affecting the output voltage when switching between discharging and charging operations. A low-pass filter is used to reduce feedback noise on the output node. A replica feedback circuit prevents current mismatch between the currents produced by the first and second current sources. The first and second current sources may be formed using programmable transistors that are adjusted by static control signals provided by programmable elements to further minimize current mismatch.

Charge pump with reduced current mismatch

A blind adaptive decision feedback equalizer technique relies on two thresholds. The first threshold is applied to the incoming sampled analog data. According to this aspect of the invention, if the signal magnitude exceeds the threshold, then it is considered valid, while if it is below the threshold, it is considered erroneous. This reduces processing, because not every sample generates an error signal. The second threshold is a block threshold that determines when the filter coefficients are updated to account for the incoming data. In accordance with this aspect of the invention, only when a certain number of errors has been accumulated are the coefficients updated. This results in a further reduction in processing.

Blind adaptive decision feedback equalizer for high-speed serial communications

Circuitry and methods for supporting serial communications over serial interconnects between circuit modules are provided. A data recovery circuit receives incoming serial data from the serial interconnect path with zero delay. The data recovery circuit includes a data sampler that samples the incoming serial data using a multiphase clock. Data samples are provided to a multiplexer that selects an optimum sampled data signal to use as a recovered data signal. The multiplexer has a control input that receives a phase pointer signal. Control circuitry in the data recovery circuit analyzes the sampled data signals and a current value of the phase pointer to compute a clock phase shift error. If the clock phase shift error exceeds a predetermined value, the phase pointer signal can be updated. The data recovery circuit may be implemented using hardwired circuitry or programmable logic.

Zero-delay serial communications circuitry for serial interconnects

A phase-locked loop includes a phase-to-digital converter that receives a first periodic input signal at a first input and a first feedback signal at a second input. The phase-to-digital converter generates digital signals. A digitally controlled oscillator includes a delay-locked loop that is responsive to the digital signals. The delay-locked loop generates a periodic output signal having an average frequency that is a product of a frequency of the first periodic input signal multiplied by a non-integer fractional number while a phase of the first periodic input signal is unchanging.

Fractional delay-locked loops

Methods and circuits are provided for producing phase-adjusted pre-emphasis and equalization. In applications in which little or no phase distortion occurs during signal transmission, propagation, or reception, linear-phase pre-emphasis or equalization can be used to reduce or eliminate phase distortion introduced by the pre-emphasis or equalization. Linear phase, constant group delay FIR filters or circuits may have odd numbers of coefficients symmetrical about the middle coefficient. In applications in which signal phase distortion occurs, linear phase or non-linear phase pre-emphasis or equalization can be used to reduce or compensate for the phase distortion. Phase compensation may be effected using FIR pre-emphasis and equalization filters and circuits. Non-linear phase FIR filters may have different numbers and combinations of coefficients.

Phase-adjusted pre-emphasis and equalization for data communication

Frequency synthesizer circuitry employs a delay line. A reference clock signal propagates through successive stages of the delay line, and the currents drawn by output buffers of all of the stages are added at a common node. The common node current is converted to a voltage, which is AC-coupled to an output buffer ring oscillator of the frequency synthesizer. The output buffer ring oscillator includes a plurality of inverters connected in a series. A feedback connection including a resistor is provided from an output node of the last inverter to an input node of the first inverter.

Frequency synthesizer circuitry employing delay line

Equalization circuitry that includes an analog equalizer and a decision feedback equalizer (DFE) is provided for high-speed backplane data communication. The analog equalizer reduces the number of taps that are required by the DFE, which lessens the error propagation of the DFE. Furthermore, the DFE includes a summing circuit and flip-flop circuitry. The flip-flop circuitry may be used as part of a phase detector by clock and data recovery circuitry. The summing circuit may further be embedded into the flip-flop circuitry to reduce the feedback path delay, thereby allowing for higher speed operation. The DFE may be extended to multiple taps by including additional flip-flops.

Methods and apparatus for equalization in high-speed backplane data communication

Systems and methods for accurately and quickly simulating link performance of a transceiver operating with any given transmission medium are provided. Accurate and quick link simulations may be provided using a link simulation platform. The link simulation platform may simulate link performance using transceiver behavioral models (e.g., transmitter and receiver behavioral models) that incorporate silicon level parameters, which parameters enable the behavioral models to substantially emulate the actual behavior of the transceiver portions of the link.

Systems and methods for simulating link performance

Phase detection circuitry in a delay-locked loop compares a periodic input signal to a feedback signal. The phase detection circuitry generates a delay signal that controls delays of the delay circuits. Two or more output signals of the delay circuits are transmitted to an input of the phase detection circuitry. The delay-locked loop can be configured so that the period of the periodic input signal divided by a delay of one of the delay circuits equals a non-integer rational number when the phase and frequency of the periodic input signal are constant. A frequency multiplier can be coupled to the delay circuits to generate a periodic output signal. The periodic output signal has an average frequency that is a product of the frequency of the periodic input signal multiplied by a fractional non-integer number when the phase and frequency of the periodic input signal are constant.

An all-digital serializer-de-serializer includes an all-digital clock multiplier unit (CMU) circuit, an all-digital clock and data recovery (CDR) circuit, a multiplexer (MUX), and a demultiplexer (DeMUX). The all-digital clock and data recovery (CDR) circuit couples to the all-digital clock multiplier unit (CMU) circuit. The multiplexer (MUX), couples to all-digital clock multiplier unit (CMU) circuit, and serializes data. The demultiplexer (DeMUX), couples to the all-digital clock and data recovery (CDR) circuit, and de-serializes data.

Apparatus for all-digital serializer-de-serializer and associated methods

A digital loop circuit&#x2014;i.e., a phase-locked loop ('PLL') or delay-locked loop ('DLL')&#x2014;having a simplified digital loop filter, is particularly well-suited for a programmable logic device (&#x201c;PLD&#x201d;). The loop filter may be a memory (e.g., a shift register) which counts the early/late or up/down signals from a phase detector or phase-frequency detector (&#x201c;error detector&#x201d;) and outputs a signal when the count exceeds a threshold. Separate integral and proportional paths of the loop may include chained shift registers, with each outputting a signal only when the previous shift register overflows into it. A digital error detector may respond nonlinearly, with outputs of different bit widths, to different amounts of phase or frequency error.

Digital loop circuit for programmable logic device

A dual-mode LVDS/CML transmitter allows a single circuit to operate as either an LVDS transmitter or a CML transmitter. The transmitter mode can be switched by activating or deactivating appropriate circuit elements, and changing the voltage or current produced by appropriate sources or sinks. This flexibility allows a single transmitter to operate well in both AC and DC coupling conditions, and facilitates interoperation with a greater variety of receivers.

Dual-mode LVDS/CML transmitter methods and apparatus

A clock data recovery loop that can be used over a wide range of data rates and maintain second-order behavior includes a nonlinear (e.g., Bang-Bang) phase detector, a charge pump, an RC loop filter, and signal generator (e.g., a voltage controlled oscillator (VCO)). At low data rates, the loop may be operated with the charge pump and loop filter with stable second-order behavior, with the resistor R of the loop filter serving as a proportional path. A separate proportional path is also provided that provides phase detector output directly to a control input of the VCO, while the resistor R of the loop filter is also bypassed. As increasing data rates give rise to third-order effects, the separate proportional path may be activated to maintain second-order behavior.

Clock data recovery loop with separate proportional path

Pre-emphasis circuitry and methods for signal transmission provide multiple levels of output signal amplification over one or more baud periods after an input signal transition. The multiple, gradually decreasing levels of output signal amplification reduce power consumption and better approximate the desired signal response.

Growing community of inventors

Ottawa, Canada

Tad Kwasniewski