Integrated Device Technology, Inc.

Other

Tacettin Isik

Daniel M Clementi

Louis F Poitras

Selcuk Sen

Jan Gazda

Robert Paul Bernardo

Siyou Weng

A house number light includes a frame defining an opening in a central portion and having a side opening along an inside face. The frame includes light sources, first and second power sources configured to provide electric power to the light sources, and a control circuit connected between the first power source and the light sources and connected between the second power source and the light sources. The control circuit electrically couples one of the first and the second power sources to the light sources at a time. If the first power source is electrically coupled to the light sources, electrical energy from the first power source passes through the control circuit to the light sources, and if the second power source is electrically coupled to the light sources, electrical energy provided by the second power source passes through the control circuit to the light sources.

House lighting device

A voltage regulator circuit includes a linear voltage regulator having a pass transistor and a first feedback from an output load, and a switching regulator having a second feedback from a voltage drop across the pass transistor. The voltage regulator further includes an efficiency monitor configured to detect the voltage drop and control predetermined steps of a duty cycle of the switching regulator based on the voltage drop.

Highly simplified switching regulator which allows very high switching frequencies

Methods for compensating the existing crystal oscillator frequencies in extended temperature ranges. Utilizing existing crystal oscillators on any system design which may have quartz crystals with associated circuitry to deliver frequency or timing reference signals and increasing the accuracy of such by additional circuitry.

Methods of frequency versus temperature compensation of existing crystal oscillators

A method and apparatus for placing quartz SAW (Surface Acoustic Wave) devices together with a clock/oscillator have been disclosed. Mounting on a single lead frame both a SAW device and an integrated circuit (IC).

Method and apparatus for placing quartz SAW devices together with clock/oscillator

A method and apparatus for externally aided self adjusting real time clock have been disclosed. A circuit having a pulse train output is coupled to an adjusting circuit, a real-time clock is coupled to the adjusting circuit, and a proportional integral derivative time processor is coupled to the adjusting circuit, and where the adjusting circuit affects the pulse train output.

Method and apparatus for externally aided self adjusting real time clock

A method and apparatus for fail-safe start-up circuit for subthreshold current sources have been disclosed.

Method and apparatus for fail-safe start-up circuit for subthreshold current sources

N-channel field effect transistor Proportional To Absolute Temperature (N-PTAT) cells are connected to a first supply voltage and P-channel field effect transistor Proportional To Absolute Temperature (P-PTAT) cells are connected to a second supply voltage. A coupling circuit connects at least one of the N-PTAT cells to at least one of the P-PTAT cells. These circuits can be used to provide a voltage reference and/or a supply voltage level detector. Related operating methods are also described.

Voltage reference and supply voltage level detector circuits using proportional to absolute temperature cells

A high voltage switch having first and second states includes an input receiving an input voltage that is greater than a supply voltage. Each of first, second, and third MOS structures of a first conductivity type has a gate, a source, and a drain. The sources and drains of each of the MOS structures are electrically coupled in series between the input and ground. An output is electrically coupled to the input. When the switch is in the first state, the gate of the first MOS structure is pulled to ground, the gate of the second MOS structure is pulled to the supply voltage, and the gate of the third MOS structure is pulled to a voltage greater than the supply voltage and less than the input voltage. When the switch is in the second state, the gates of all of the MOS structures are pulled to the supply voltage.

High voltage switch utilizing low voltage MOS transistors with high voltage breakdown isolation junctions

A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal. The driver includes first, second, third and fourth n-type metal oxide semiconductor (NMOS) that are cross-connected between the reduced voltage and the first and second driver outputs or a constant voltage internal ground. When the second input is high, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the constant voltage ground.

Low power output driver

A clock circuit generates a reference clock signal based on a resonant frequency of a crystal, generates thermometer-coded signals based on the reference clock signal, and generates a pulse train based on the thermometer-coded signals. The pulse train has a frequency that is a multiple of the frequency of the reference clock signal. Additionally, the clock circuit includes a phase-lock loop for generating an output clock signal based on the pulse train and aligning a phase of the output clock signal with pulses in the pulse train. In various embodiments, the frequency of the reference clock signal is the same as the resonant frequency of the crystal and the frequency of the output clock signal is a multiple of the resonant frequency of the crystal. Moreover, reference clock signal and the output clock signal each have a long-term jitter based on the precision of the resonant frequency of the crystal.

Clock circuit for reducing long term jitter

A method and apparatus for self gate pumped NMOS high speed switch have been disclosed.

Method and apparatus for self gate pumped NMOS high speed switch

A ring oscillator circuit having an odd plurality of inverter stages (i.e., 2N+1 stages). In accordance with one embodiment of the present invention, only one of the inverter stages is operated in response to a variable input voltage, while the remaining inverter stages are operated in response to a highly filtered constant input voltage. The inverter stages that operate in response to the constant input voltage oscillate at a base frequency. The inverter stage that operates in response to the variable input voltage causes the frequency of the output signal to deviate from the base frequency by an amount determined by the variable input voltage. In this manner, the variable voltage inverter stage implements frequency control for the ring oscillator. The gain of the ring oscillator circuit is reduced by a factor of (2N+1) with respect to the gain of a conventional ring oscillator.

Simple technique for reduction of gain in a voltage controlled oscillator

A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal. The driver includes first, second, third and fourth n-type metal oxide semiconductor (NMOS) that are cross-connected between the reduced voltage and the first and second driver outputs or ground. When the second input is high, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the internal ground.

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Saratoga, CA, United States of America

Tacettin Isik