Cadence Design Systems, Inc.

Praesagus, Inc.

Lucira Health, Inc.

Other

Taber H Smith

David Allan White

Vikas Mehrotra

Frank B Myers, Iii

Clay David Reber

Li J Song

Faisal S Maniar

Zhan-Zhong Yao

Vishal Sarin

Srinivas Rao Doddi

Emmanuel Drege

Rachid Salik

Hao Ji

Purackal Mammen Mammen

Ron Pyke

Ming Liu

JenPin Weng

Hao Jl

Brian Lee

This invention relates generally to devices, systems, and methods for performing biological assays by using indicators that modify one or more optical properties of the assayed biological samples. The subject methods include generating a reaction product by carrying out a biochemical reaction on the biological sample introduced into a device and reacting the reaction product with an indicator capable of generating a detectable change in an optical property of the biological sample to indicate the presence, absence, or amount of analyte suspected to be present in the sample.

Multiplexed biological assay device with electronic readout

In one aspect, A method for computing neural network computation includes the step of, providing plurality of neurons, coupled with a plurality of inputs, through a plurality of synapses. Each neuron output is given by an equation &#x3a3;(X*Y)+b. X*Ycomprises the ith synapse of the neuron. Xcomprises a set of Xinput vectors. Each Xinput vector is translated into an equivalent electrical signal for an ith corresponding synapse of the plurality of neurons, Ycomprises a set of Yi weight vectors, wherein each Yweight vector comprises a parameter for the ith corresponding synapse of the plurality of neurons. Each synapse is a sub-system and the sub-system comprises a negative vector neural circuit, a positive vector neural circuit, and a set of four non-volatile memory weight cells for computation. The method includes the step of identifying the input vector x as a positive input vector or a negative input vector.

Methods and systems of implementing positive and negative neurons in a neural array-based flash memory

Disclosed is a method, system, and computer program product for performing predictions for an electronic design. Embodiments of the invention allow the ability to efficiently update the model predictions at a later time once previously incomplete blocks are completed. Predictions can be efficiently updated after block designs are updated (e.g. after correcting problems detected from model predictions).

Method and system performing circuit design predictions

A method, system, and computer program product are disclosed for performing RC extraction. The present approach can consider multiple types of manufacturing processes, and allows location-based prediction data to be used in the context of net-based analysis. RC extraction can be more accurately performed based upon net-specific top and bottom adjustments to thickness prediction that are location-based. The net-based prediction data can be used for other purposes as well, such as to perform electrical hotspot analysis, to visually display physical properties of the nets, or allow queries for other data analysis purposes.

Method and system performing RC extraction

Disclosed are a method, a system, and a computer program product for implementing hotspot detection, repair, and optimization of an electronic circuit design, which, in some embodiments, defines, identifies criteria for hotspots/metrics or optimization objective function; performs the initial hotspot or metric prediction; identifies correction candidate(s); applies a correction candidate to the electronic circuit design; and determines whether the outcome of applying the correction candidate is acceptable. The method or the system identifies custom correction candidate(s) or custom command(s) and identifies one or more hints for the predicted hotspots or metrics; provides a single architecture to use a first model for hotspot identification/correction and a second model for design check; and provides the capability to apply a correction for a hotspot or metric, evaluate the effectiveness of the correction on the fly, and revert any changes made to the electronic circuit design by the correction.

Methods, systems, and computer program product for implementing hotspot detection, repair, and optimization of an electronic circuit design

A method, system, and computer program product are disclosed for performing RC extraction from the perspective of the block level. A translation mechanism is employed to convert from a full-chip design domain to a block-level design domain. This allows model-based prediction results to be used in the early design implementation flow when parasitic RC and timing extractions are performed, where the model-based prediction results relate to predictions of manufacturing variations such as thickness and topography.

Method and system performing block-level RC extraction

A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.

Characterization and reduction of variation for integrated circuits

An electronic design is generated for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit. The generating includes adjusting the electronic design based on predictions of topographical and topographical-related feature dimension variations by a pattern-dependent model. An RC extraction tool is used in conjunction with the generating and adjusting of the electronic design. The process includes a fabrication process that will impart topographical variation to the integrated circuit and a lithography or etch process. Placement attributes for elements of the integrated circuit are determined.

Electronic design for integrated circuits based on process related variations

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.

Methods and systems for implementing dummy fill for integrated circuits

Variations are characterized in feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that produces topographical variation in the integrated circuit, the variations in feature dimension being caused by the topographical variations. The process includes lithography or etch. Predicted characteristics are verified to conform to the design, the characteristics including feature dimensions or electrical characteristics. A process is selected for use in fabricating the integrated circuit based on the relative predicted variations. Chip-level features of a design of an integrated circuit are verified for manufacture within focus limitations of a lithographic tool. Whether a design of a level of an integrated circuit can be lithographically imaged in accordance with the design is predicted, and if it cannot be, the design or processing parameters are adjusted so that it can be.

Characterization and verification for integrated circuit designs

Dummy fill for integrated circuits

A pattern-dependent model is used to predict characteristics of an integrated circuit that is to be fabricated in accordance with a design by a process. The process includes (a) a fabrication process that will impart topographical variation to the integrated circuit and (b) a lithography or etch process, the lithography or etch process using a mask produced from the design. The lithography or etch process and the fabrication process interact to cause the predicted characteristics to differ from the design. The mask is adjusted in response to characteristics predicted by the model, to reduce the effect of the interacting of the lithography or etch process and the fabrication process. A location on an integrated circuit is predicted for which a lithography tool would not produce a satisfactory feature dimension without a degree of adjustment of the tool during fabrication to accommodate a focus limitation of the tool, and the design of at least one mask derived from the design is adjusted to enable the lithography tool to produce a satisfactory feature dimension at the locations. A virtual adjustment is effected of a distance of a lithographic tool from a location in a region of a wafer, the virtual adjustment being effected by using a mask having a mask layout that has been generated based on a pattern-dependent model prediction that the location in the region of the wafer would not otherwise have a satisfactory feature dimension due to a focus limitation of the lithographic tool. A pattern-dependent model is used to predict topography variations that will occur in an integrated circuit as a result of processing up to a predetermined lithographic process step, and designs of masks used in the lithographic process step are adjusted to accommodate the topography variations.

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Fremont, CA, United States of America

Taber H Smith