Freescale Semiconductor,inc.

Nxp Usa, Inc.

Advanced Micro Devices Corporation

Tab Allen Stephens

Perry H Pelley

Michael B McShane

Leo Mathew

Bich-Yen Nguyen

Mark Douglas Hall

Voon-Yew Thean

Kevin John Hess

Paul Grudowski

Marilyn I Wright

Kurt H Junker

John M Grant

Brian J Goolsby

Kyle W Patterson

Douglas M Reber

Edward K Theiss

Srikanteswara Dakshiina-Murthy

Marius K Orlowski

Dina H Triyoso

Gregory S Spencer

Rode R Mora

Victor H Vartanian

Marc A Rossow

Jian Feng Chen

Mehul D Shroff

Ramachandran Muralidhar

Olubunmi O Adetutu

Chun-Li Liu

Alexander Barr

Shawn George Thomas

Ted R White

Vishal P Trivedi

Bruce E White

Stanley Michael Filipiak

Thien T Nguyen

Dharmesh Jawarani

Tim V Pham

Matthew Thomas Herrick

Tien Ying Luo

Chong-Cheng Fu

Yongjoo Jeon

David C Sing

John J Hackenberg

Anne M Vandooren

Charles F King

Lakshmanna Vishnubholta

Daniel G Tekleab

An integrated circuit optical die test interface and associated testing method are described for using scribe area optical mirror structures () to perform wafer die tests on MEMS optical beam waveguide () and optical circuit elements () by perpendicularly deflecting optical test signals () from the scribe area optical mirror structures () into and out of the plane of the integrated circuit die under test () and/or production test die ().

Optical die test interface with separate voltages for adjacent electrodes

An integrated circuit optical backplane die and associated semiconductor fabrication process are described for forming optical backplane mirror structures for perpendicularly deflecting optical signals out of the plane of the optical backplane die by selectively etching an optical waveguide semiconductor layer () on an optical backplane die wafer using an orientation-dependent anisotropic wet etch process to form a first recess opening () with angled semiconductor sidewall surfaces () on the optical waveguide semiconductor layer, where the angled semiconductor sidewall surfaces () are processed to form an optical backplane mirror () for perpendicularly deflecting optical signals to and from a lateral plane of the optical waveguide semiconductor layer.

Optical backplane mirror

A high density, low power, high performance information system, method and apparatus are described in which an integrated circuit apparatus includes a first integrated circuit link element () and a redundant integrated circuit link element () connected in parallel between first and second deflectable MEMS switches (--) which are connected in a signal path and controlled to deselect the first integrated circuit link element () and connect the redundant integrated circuit link element () in the signal path in response to a two-state control signal provided to the first and second deflectable MEMs switches which identifies the first integrated circuit link element as being defective.

Optical redundancy

A high density, low power, high performance information system, method and apparatus are described in which an integrated circuit apparatus includes a plurality of deflectable MEMS optical beam waveguides (e.g.,) at each die edge which are each formed with an optical beam structure () which is encapsulated by a waveguide beam structure () to extend into a deflection cavity () and which is surrounded by a plurality of deflection electrodes (-) that are positioned on walls of the deflection cavity () to provide two-dimensional deflection control of each deflectable MEMS optical beam waveguide in response to application of one or more deflection voltages to provide optical communications (e.g.,) between different die.

Integration of a MEMS beam with optical waveguide and deflection in two dimensions

A method of manufacturing a microelectronic assembly () and a microelectronic device () that include a stacked structure (). The stacked structure includes a heat spreader (), at least one die () thermally coupled to at least a portion of one side of the heat spreader, at least one other die () thermal coupled to at least a portion of an opposite side of the heat spreader, at least one opening () in the heat spreader located in a region of between the two die, an insulator () disposed in the at least one opening, and electrically conductive material () in an insulated hole () in the insulator. The heat spreader allows electrical communication between the two die through the opening while the insulator isolates the electrically conductive material and the heat spreader from each other.

Microelectronic assembly having a heat spreader for a plurality of die

A first semiconductor device die is provided having a bottom edge incorporating a notch structure that allows sufficient height and width clearance for a wire bond connected to a bond pad on an active surface of a second semiconductor device die upon which the first semiconductor device die is stacked. Use of such notch structures reduces a height of a stack incorporating the first and second semiconductor device die, thereby also reducing a thickness of a semiconductor device package incorporating the stack.

Wirebond recess for stacked die

An optical die probe wafer testing circuit arrangement and associated testing methodology are described for mounting a production test die () and surrounding scribe grid () to a test head () which is positioned over a wafer () in alignment with a die under test () and surrounding scribe grid (), such that one or more optical deflection mirrors () in the test head scribe grid () are aligned with one or more optical deflection mirrors () in the scribe grid () for the die under test () to enable optical die probe testing on the die under test () by directing a first optical test signal () from the production test die (), through the first and second optical deflection mirrors (e.g.,) and to the first die.

Optical wafer and die probe testing

An electronic assembly includes a processor die assembly, a first die assembly, and a second die assembly. The first die assembly is positioned on a first side of the processor die assembly. The second die assembly is positioned on a second side of the processor die assembly opposite the first side of the processor die assembly. Through-die vias couple the first and second die assemblies to the processor die assembly.

Techniques for reducing inductance in through-die vias of an electronic assembly

A high density, low power, high performance information system, method and apparatus are described in which perpendicularly oriented processor and memory die stacks () include integrated deflectable MEMS optical beam waveguides (e.g.,) at each die edge to provide optical communications (-) in and between die stacks by supplying deflection voltages to a plurality of deflection electrodes (-) positioned on and around each MEMS optical beam waveguide (-) to provide two-dimensional alignment and controlled feedback to adjust beam alignment and establish optical communication links between die stacks.

Communication system die stack

A high density, low power, high performance information system, method and apparatus are described in which a laser source () on a first die () generates a source light beam of unmodulated monochromatic coherent light () for distribution via optical beam routing structures (e.g.,) to a plurality of receiving die (), each of which includes its own modulator (e.g.,) for optically receiving at least a portion of the source light beam () from the first die and generating therefrom an output source light beam of modulated monochromatic coherent light () which is encoded at said modulator in response to electrical signal information.

Die stack with optical TSVs

A semiconductor device comprising a substrate, a power bus, a heat source circuit, a heat sensitive circuit, and a plurality of electrically and thermally conductive through-silicon-vias (TSVs) in the substrate. The TSVs are electrically coupled to the power bus and positioned between the heat source circuit and the heat sensitive circuit to absorb heat from the heat source circuit.

Methods and structures for reducing heat exposure of thermally sensitive semiconductor devices

A stacked semiconductor device includes a first and second semiconductor device having a first major surface and a second major surface opposite the first major surface, the first major surface of the first and second semiconductor devices include active circuitry. The first and second semiconductor devices are stacked so that the first major surface of the first semiconductor device faces the first major surface of the second semiconductor device. At least one continuous conductive via extends from the second major surface of the first semiconductor device to the first major surface of the second semiconductor device. Conductive material fills a cavity adjacent to the contact pad and is in contact with one side of the contact pad. Another side of the contact pad of the first semiconductor device faces and is in contact with another side of the contact pad of the second semiconductor device.

Stacked semiconductor devices

A microelectronic assembly () and a microelectronic device () include a stacked structure (). The stacked structure includes a heat spreader (), at least one die () thermally coupled to at least a portion of one side of the heat spreader, at least one other die () thermal coupled to at least a portion of an opposite side of the heat spreader, at least one opening () in the heat spreader located in a region of between the two die, an insulator () disposed in the at least one opening, and electrically conductive material () in an insulated hole () in the insulator. The heat spreader allows electrical communication between the two die through the opening while the insulator isolates the electrically conductive material and the heat spreader from each other.

An anti-counterfeiting security circuit is incorporated into an authentic integrated circuit device to induce failure in a counterfeited integrated circuit device by forming the security circuit (e.g.,) with one or more operatively inert high-k metal gate transistors (e.g., HKMG PMOS) having switched or altered work function metal layers () where the security circuit defines a first electrical function with the one or more operatively inert high-k metal gate transistors and defines a second different electrical function if the one or more operatively inert high-k metal gate transistors were instead fabricated as operatively functional high-k metal gate transistors of the first polarity type with a work function metal layer of the first polarity type, the security circuit would define a second different electrical function.

Gate security feature

An electric device with vias that include dielectric structures to prevent conductive material in the vias from electrically connecting conductive structures on a top of the vias with conductive structures on the bottom of the vias. The dielectric structures are formed in selected vias where other vias do not include the dielectric structures.

Semiconductor devices with nonconductive vias

Growing community of inventors

Austin, TX, United States of America

Tab Allen Stephens