Intel Corporation

Tahoe Research, Ltd.

Taarinya Polepeddi

Raj K Ramanujan

Muthukumar Swaminathan

Bill Nale

Tessil Thomas

Mohan J Kumar

Glenn J Hinton

Rajat Agarwal

David Zimmerman

Kai Cheng

Dimitrios Ziakas

Bassam N Coury

Camille C Raad

Muthukuman P Swaminathan

David J Zimmerman

A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as 'far memory.' Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as 'near memory.'

Apparatus and method for implementing a multi-level memory hierarchy

A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.

Memory channel that supports near memory and far memory access

A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol

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Saratoga, CA, United States of America

Taarinya Polepeddi