Vishay General Semiconductor, Inc.

Ta-Te Chou

Yong-Qi Tian

Xian Li

Xiong-Jie Zhang

Hai Fu

Hui-Ying Ding

Yun Zhang

Hong-Yun He

Li-Zhu Hao

A semiconductor device mountable to a substrate is provided. The device includes a semiconductor package having at least one semiconductor die, an electrically conductive attachment region, and a packaging material in which is embedded the semiconductor die and a first portion of the electrically conductive attachment region contacting the die. A metallic shell encloses the embedded semiconductor die and the first portion of the electrically conductive attachment region.

Semiconductor device and method for manufacturing a semiconductor device

A semiconductor device mountable to a substrate includes a semiconductor die and an electrically conductive lead frame having first and second end portions and a first attachment surface and a second attachment surface. The die electrically contacts the first end portion of the lead frame on the first attachment surface. An externally exposed housing encloses the semiconductor die and the first end portion of the lead frame, said housing including a metallic plate facing the second attachment surface of the lead frame.

Semiconductor device having improved heat dissipation capabilities

Bridge rectifier package with heat sink

A semiconductor device mountable to a substrate includes a semiconductor die and an electrically conductive attachment region having a first attachment surface and a second attachment surface. The first attachment surface is arranged for electrical communication with the semiconductor die. A housing at least in part encloses the semiconductor die and the interlayer material. The housing has a recess disposed through the second attachment surface of the electrically conductive attachment region. A dielectric, thermally conductive interlayer material is located in the recess and secured to the housing. A metallic plate is located in the recess and secured to the interlayer material.

Semiconductor device and method for manufacturing a semiconductor device having improved heat dissipation capabilities

An apparatus and method for a two semiconductor device package where the semiconductor devices are connected in electrical series. The first device is mounted P-side down on an electrically conductive substrate. Non-active area on the P side is isolated from the electrically conductive substrate. The second device is mounted P-side up at a spaced apart location on the substrate. Opposite sides of each are electrically connected to leads to complete the series connection of the two devices. A method of manufacturing such a package includes providing an electrically conductive lead frame, mounting one device P-side up and flipping the other device and mounting it P-side down on the lead frame with non-active area of the P side isolated from the lead frame, and connecting the other side of each device to separate leads. Isolation of the non-active area of the P side of the device can be through modification of the substrate or lead frame surface by grooves or raised portions. Alternatively, it can be by adding an electrically isolating coating on the non-active area of the P-side of a semiconductor device to allow it to be mounted P side down on an electrically conductive substrate or mounting location without modification to the substrate or lead frame.

Apparatus and method for series connection of two die or chips in single electronics package

Bridge rectifier package

A semiconductor device mountable to a substrate is provided. The device includes a semiconductor die and an electrically conductive attachment region having a first attachment surface and a second attachment surface. The first attachment surface is arranged for electrical communication with the semiconductor die. An interlayer material is formed on the second attachment surface of the electrically conductive attachment region. The interlayer material is a thermally conductive, dielectric material. A housing at least in part encloses the semiconductor die and the interlayer material.

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Taipei, Taiwan

Ta-Te Chou