Other

Tron Future Tech Inc.

Ipgreat Incorporated

Htc Corporation

National Yang Ming Chiao Tung University

Walsin Lihwa Corporation

Ta-Shun Chu

Yuan-Ju Chao

Yu-Jiu Wang

Yue Ming Wu

Chun-Chieh Peng

Hao-Chung Chou

Ta-Chun Pu

Chun-Yih Wu

Long-Sun Huang

Li Han Chang

Chao-Sen Chang

Son-Nan Chen

A radio frequency (RF) transmitter includes a radiating element, a chip and a phase shifting circuit. The radiating element is arranged to receive a plurality of electrical signals to produce an RF output signal. The chip includes an amplifier circuit. The amplifier circuit is configured to amplify an RF input signal to generate a plurality of amplified signals at a plurality of output terminals, respectively. The phase shifting circuit is located outside the chip, and coupled to the output terminals and the radiating element. The phase shifting circuit is arranged to phase shift the amplified signals, and accordingly generate the electrical signals fed to the radiating element. The phase shifting circuit and the radiating element are formed on a same substrate.

RF transmitter and method for emitting RF output signal

A method for manufacturing a first radio-frequency (RF) device, including: receiving a substrate having the first RF device, wherein the first RF device has a signal port for receiving or transmitting RF signals with an input impedance greater than ten times an input impedance of a testing tool; causing a probe assembly to connect to the signal port and the testing tool; and causing the probe assembly to connect to a first terminal of a resistive element having a resistance equal to the input impedance.

Probe assembly, system and method for testing rf device of phased array antenna

A signal converting apparatus includes a comparing device, a first digital-slope quantizer, and a second digital-slope quantizer. The comparing device having a first input terminal and a second input terminal for receiving a first received signal and a second received signal, and for generating an output signal at an output port. The first digital-slope quantizer generates a first set of digital signals to monotonically adjust the first received signal and the second received signal at the first input terminal and the second input terminal during a first phase according to a first quantization unit. The second digital-slope quantizer generates a second set of digital signals to monotonically adjust the first received signal and the second received signal at the first input terminal and the second input terminal during a second phase after the first phase according to a second quantization unit.

Signal converting apparatus and related method

A signal distribution system includes: a first signal divider arranged to generate a first output oscillating signal according to a first input oscillating signal; a second signal divider arranged to generate a second output oscillating signal according to the first input oscillating signal; a first transmitting channel coupled to the first signal divider and the second divider for transmitting the first input oscillating signal to the first signal divider and the second signal divider; and a second transmitting channel coupled to the first signal divider and the second divider for transmitting a second input oscillating signal to the first signal divider and the second signal divider; wherein the first input oscillating signal has a first frequency, the second input oscillating signal has a second frequency, and the second frequency is smaller than the first frequency.

Signal distribution system, and related phased array radar system

A signal divider includes: a dividing circuit arranged to generate an output oscillating signal according to a first input oscillating signal; and a signal generating circuit, coupled to the dividing circuit, for generating an injection signal to the dividing circuit. The dividing circuit is arranged to generate the output oscillating signal with a predetermined phase according to the injection signal and the first input oscillating signal.

Signal divider, signal distribution system, and method thereof

A signal converting apparatus includes a comparing device, a first digital-slope quantizer, and a second digital-slope quantizer. The comparing device has a first input terminal and a second input terminal for receiving a received signal and an adjustable reference voltage respectively, and for generating an output signal at an output port. The first digital-slope quantizer is coupled to the output port and the second input terminal for generating a first set of digital signals to monotonically adjust the adjustable reference voltage at the second input terminal during a first phase according to a first quantization unit. The second digital-slope quantizer is coupled to the output port and the second input terminal for generating a second set of digital signals to monotonically adjust the adjustable reference voltage at the second input terminal during a second phase after the first phase according to a second quantization unit.

Signal converting apparatus

Systems and methods of restraining reverse engineering process for analog integrated circuit use techniques of adding dummy devices, device fragmentation, increasing bus width, employing different layouts for the same circuit element and mixing different types of passive devices increase complexity and makes the layout floorplan more difficult to be extracted for the reverse engineering. The system adds dummy devices and ensures the extra devices and capacitance do not affect the target circuit performance.

System and method for anti reverse engineering for analog integrated circuit

A wireless transceiver includes: a switching amplifier having first, second and power ports; and a current provider. The current provider provides a current to the power port, and further provides an impedance to the power port such that an impedance of the switching amplifier at the second port matches an impedance of an antenna coupled to the second port. The switching amplifier simultaneously amplifies a transmit signal input received at the first port to generate an output signal at the second port for receipt by the antenna, and mixes a receive signal received at the second port from the antenna with the transmit signal input to generate, at the power port, another output signal having a frequency lower than that of the receive signal.

Wireless transceiver

A method of increasing SAR ADC conversion rate and reducing power consumption by employing a new timing scheme and minimizing timing delay for each bit-test during binary-search process. The high frequency clock input requirement is eliminated and higher speed rate can be achieved in SAR ADC.

High speed SAR ADC using comparator output triggered binary-search timing scheme and bit-dependent DAC settling

A current steering converter fabricated using a predetermined integrated circuit technology includes a unary portion having one or more current sources and a binary portion including a plurality of switches controlled by a decoder, the switches coupled to a converter output; and a plurality of devices commonly connected at a first end and coupled to each respective switch at a second end, wherein each device size comprises (W/L)*M, where W/L is a width and length of the device and M is an integer representing multiple number.

System and method of minimizing differential non-linearity (DNL) for high resolution current steering DAC

A method of detecting clock duty cycle and adjusting clock duty cycle to achieve a clock with low jitters, low noise, high common mode rejection and high power supply rejection for sampling circuit. Adjusting the duty cycle of the sampling clock can enhance data converter's performance.

Programmable duty-cycle low jitter differential clock buffer

A data converter includes a single-end capacitive digital to analog converter (DAC); a transconductance (GM) buffer having an output, a positive input coupled to the DAC and a negative input coupled to the output; a resistor and a capacitor load in parallel coupled to the output at one terminal and to ground at the other terminal. The developed architecture of comprising single end capacitive DAC and GM-based buffer provides fast conversion rate, low current consumption, small silicon area and wide supply range for general-purpose auxiliary DAC applications.

Appapatus and method for fast conversion, compact, ultra low power, wide supply range auxiliary digital to analog converters

A high resolution timing device is provided. The high resolution timing device includes a first and a second clock delay circuits. The first clock delay circuit receives an input reference clock signal to generate a first multiple frequency output clock signal, divide the first multiple frequency output clock signal to generate a first original frequency output clock signal and perform a clock-delaying process thereon according to the first multiple frequency output clock signal to generate first clock-delayed signals. The second clock delay circuit receives one of the first clock-delayed signals to generate a second multiple frequency output clock signal, divide the second multiple frequency output clock signal to generate a second original frequency output clock signal and perform the clock-delaying process thereon according to the second multiple frequency output clock signal to generate second clock-delayed signals.

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Hsinchu, Taiwan

Ta-Shun Chu