Taiwan Semiconductor Manufacturing Comp. Ltd.

Ta-Pen Guo

Jean-Pierre Colinge

Carlos H Diaz

Li-Chun Tien

Lee-Chung Lu

Kuo-Cheng Ching

Chung-Cheng Wu

Chien-Ying Chen

Chih-Hao Wang

Hsiang-Jen Tseng

Yung-Chin Hou

Shyue-Shyh Lin

Min Cao

Ali Keshavarzi

Yi-Hsiung Lin

Chih-Liang Chen

Tzu-Chiang Chen

Hung-Li Chiang

Stefan Rusu

Chao-Ching Cheng

I-Sheng Chen

Shang-Chih Hsieh

Yu-Lin Yang

Szu-Wei Huang

Nick Samra

Jiann-Tyng Tzeng

Wei-Yu Chen

Sang Hoo Dhong

Kuo-Nan Yang

Jung-Chan Yang

Chi-Lin Liu

Ming-Hsiang Song

Jerry Chang-Jui Kao

Ming-Hsien Lin

Chun-Hui Tai

Ping Chung Li

Yu-Ming Lin

Yee-Chia Yeo

Yen-Ming Chen

Zhiqiang Wu

Ting-Wei Chiang

Kuo-Ji Chen

David Barry Scott

Ken-Ichi Goto

Ting Yu Chen

Shyh-Wei Wang

Ming-Zhang Kuo

Wei Yu Ma

Sheng-Jier Yang

Guru Prasad

Shu-Hui Sung

Shu-Min Chen

Ka Hing Fung

Hsien-Wei Chen

Hao-Yi Tsai

Chih-Chiang Chang

Yi-Kan Cheng

Yuan-Te Hou

Yi-Hsun Chiu

Osamu Takahashi

Cheng-Chung Lin

Fang-Tsun Chu

Ting-Wei Chang

Guang-Cheng Wang

Jung-chan Yang

Mei-Hui Huang

Ting-Yu Chen

Jen-Hang Yang

Ramakrishnan Krishnan

Helen Shu-Hui Chang

Sang Hoo Dong

Kushare Mangesh Babaji

Sheng-Hsin Chen

Chien-ying Chen

Sang-Hoo Dhong

A semiconductor device includes a first power rail configured to supply a first voltage, a second power rail configured to supply a second voltage different from the first voltage, and a first cell arranged in a first row between the first and second power rails. The first cell has a first first-type active region and a first second-type active region. The semiconductor device further includes a second cell having a second first-type active region and a second second-type active region, wherein the second first-type active region extends in a second row and a third row on a first side of the first row. The semiconductor device also includes a third cell including a first portion and a second portion, wherein the first portion and the second portion are arranged on two sides of the first cell.

Semiconductor device including standard cell having split portions

A semiconductor device includes a first power rail and a second power rail; a third power rail and a fourth power rail, the fourth power rail aligned with the third power rail in a column direction; a first cell arranged between the first power rail and the second power rail; a second cell arranged between the first power rail and the third power rail; and a dummy fin structure extending in the row direction and overlapped with the fourth power rail, wherein the dummy fin structure is configured as a non-functional device. A first active region of the first cell includes a first width in the column direction greater than a second width, in the column direction, of a second active region in the second cell.

Semiconductor device including standard cells with combined active region

An IC device includes first through third active areas extending in a first direction and a first gate structure extending perpendicular to and overlying each of the first through third active areas. Each of the first through third active areas includes a first portion adjacent to the first gate structure in the first direction and a second portion adjacent to the first portion and including an endpoint of the corresponding active area, the first active area is positioned between the second and third active areas and includes the endpoint positioned under the first gate structure, and each of the second and third active areas includes the endpoint positioned away from the gate structure in a second direction opposite to the first direction.

Integrated circuit device and method

A semiconductor device includes a transistor layer, a first via layer over the transistor layer, a first metallization layer over the first via layer, the first metallization layer including first conductors having long axes extending substantially in a first direction, a second via layer over the first metallization layer, and a conductive deep via extending in the second via layer, the first metallization layer, and the first via layer. The first conductors represent a majority of conductive material in the first metallization layer, and a size of the deep via in the first direction in the first metallization layer is substantially less than a minimum length of the first conductors in the first metallization layer.

Semiconductor device including deep vias

A semiconductor device includes a plurality of standard cells. The plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. The first group of standard cells and the second group of standard cells are arranged in a column direction. A cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.

Semiconductor device including standard cells

An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

Integrated circuits and manufacturing methods thereof

A flip flop standard cell that includes a data input terminal configured to receive a data signal, clock input terminal configured to receive a clock signal, a data output terminal, and a latch. A bit write circuit is configured to receive a bit write signal. The received data signal is latched and provided at the output terminal in response to the bit write signal and the clock signal. A hold circuit is configured to receive a hold signal, and the received data signal is not latched and provided at the data output terminal in response to the hold signal and the clock signal.

Flip flop standard cell

A method of manufacturing a semiconductor device includes: generating a design data of the semiconductor device; and generating a design layout according to the design data. The design layout includes: a first power rail; a second power rail; a first cell including a first first-type active region and a first second-type active region, wherein a first cell height of the first cell is defined as a pitch between the first power rail and the second power rail; a second cell having a second first-type active region and a second second-type active region; and a third cell having a first portion and a second portion arranged in the second row and a fourth row, respectively.

A method of manufacturing a semiconductor device includes forming via structures in a first via layer over a transistor layer, the forming the via structures in the first via layer including forming a first via structure in the first via layer, the first via structure being included in a first deep via arrangement; forming conductive segments in a first metallization layer over the first via layer, the forming the conductive segments in the first metallization layer including forming M_1st routing segments at least a majority of which, relative to a first direction, have corresponding long axes with lengths which at least equal if not exceed a first permissible minimum value for routing segments in the first metallization layer; and forming an M_1st interconnection segment having a long axis which is less than the first permissible minimum value, the M_1st interconnection segment being included in the first deep via arrangement.

Method of forming semiconductor device including deep vias

A semiconductor device includes a first power rail, a second power rail, and a first cell. The first cell has a first first-type active region and a first second-type active region, and a first cell height of the first cell is defined as a pitch between the first power rail and the second power rail. The semiconductor device further includes a second cell having a second first-type active region and a second second-type active region, wherein the second first-type active region extends in a second row and a third row on a first side of the first row and has a first width in the column direction greater than a second width of the first first-type active region in the column direction. The semiconductor device also includes a third cell having a first portion and a second portion arranged in the second row and a fourth row, respectively.

An IC device includes a first active area extending away from a first endpoint in a first direction, a second active area extending away from a second endpoint in the first direction, a third active area positioned between the first and second active areas, and a gate structure perpendicular to the first through third active areas. The gate structure overlies each of the first and second endpoints and the third active area, and the third active area extends away from the gate structure in a second direction opposite the first direction.

A semiconductor device includes a first and a second power rails extending in a row direction, a third power rail extending in the row direction between the first and second power rail, and a first cell arranged between the first second power rails. A cell height of the first cell in a column direction perpendicular to the row direction is equal to a pitch between the first and second power rails. The semiconductor device also includes a second cell arranged between the first and third power rails. A cell height of the second cell in the column direction is equal to a pitch between the first and third power rails. A first active region of the first cell includes a first width in the column direction greater than a second width, in the column direction, of a second active region in the second cell.

A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.

Cell of transmission gate free circuit and integrated circuit layout including the same

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Taipei, Taiwan

Ta-Pen Guo