Winbond Electronics Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

Windbond Electronics Corp.

Ta-Lee Yu

Chau-Neng Wu

Shi-Tron Lin

Wei-Fan Chen

Jian-Hsing Lee

Chung-Yu Wu

Ming-Dou Ker

Konrad Kwang-Leei Young

Shui-Hung Chen

Ling-Yen Yeh

Chien-Chang Huang

Yung-Chow Peng

Jiaw-Ren Shih

Shyh-Chyi Wong

Shien-Yang Wu

Shu-Chuan Lee

Alex Wang

Fu-Chien Chiu

Kow-Liang Wen

Yang-Sen Yeh

Chau Neng Wu

Yang Sen Yeh

Yu Chen Lin

Frank S-t Lin

Tao Cheng

The invention describes the fabrication and structure of an ESD protection device for integrated circuit semiconductor devices with improved ESD protection and resiliency. A vertical bipolar npn transistor forms the basis of the protection device. To handle the large current requirements of an ESD incident, the bipolar transistor has multiple base and emitter elements formed in an npn bipolar array. To assure turn-on of the multiple elements of the array the emitter fingers are continuously or contiguously connected with an unique emitter design layout. The contiguous emitter design provides an improved electrical emitter connection for the device, minimizing any unbalance that can potentially occur when using separate emitter fingers and improving the ability for the simultaneous turn on of the multiple emitter-base elements. The emitter is contained within the footprint of the collector elements, and enables containment of device size, therefore minimizing device capacitance characteristics important in high speed circuit design. Other embodiments of the invention use variations in the structure of the common contiguous emitter conductor as well as different base conductor structure layouts.

Bipolar ESD protection structure

A novel device structure and process are described for an SCR ESD protection device used with shallow trench isolation structures. The invention incorporates an SCR device with all SCR elements essentially contained within the same active area without STI elements being interposed between the device anode and cathode elements. This enhances ESD performance by eliminating thermal degradation effects caused by interposing STI structures, and enhances the parasitic bipolar characteristics essential to ESD event turn on. Enabling this unique design is the use of an insulation oxide surface feature which prevents the formation of contact salicides in unwanted areas. This design is especially suited to silicon-on-insulator design, as well as conventional SCR and LVTSCR designs.

SCR-ESD structures with shallow trench isolation

A novel device structure and process are described for an SCR ESD protection device used with shallow trench isolation structures. The invention incorporates polysilicon gates bridging SCR diode junction elements and also bridging between SCR elements and neighboring STI structures. The presence of the strategically located polysilicon gates effectively counters the detrimental effects of non-planar STI 'pull down' regions as well as compensating for the interaction of silicide structures and the effective junction depth of diode elements bounded by STI elements. Connecting the gates to appropriate voltage sources such as the SCR anode input voltage and the SCR cathode voltage, typically ground, reduces normal operation leakage of the ESD protection device.

Silicon controlled rectifier ESD structures with trench isolation

A method to form transistors having improved ESD performance in the manufacture of an integrated circuit device is achieved. The method includes providing a SOI substrate with a doped silicon layer and a buried oxide layer. The doped silicon layer has a first conductivity type and overlies the buried oxide layer. Ions are implanted into the SOI substrate to form higher concentration regions in the doped silicon layer. The higher concentration regions have the first conductivity type and are formed substantially below the top surface of the doped silicon layer. MOS gates are formed. These MOS gates include an electrode layer overlying the doped silicon layer with a gate oxide layer therebetween. Source and drain regions are formed in the doped silicon layer to complete the transistors in the manufacture of the integrated circuit device. The source and drain regions contact the higher concentration regions and have a second conductivity type.

Method of fabricating an ESD device on SOI

A seal ring structure having an electrostatic discharge protection function, suitable for a conductive first-type substrate which has a bias provided by a second power source. The new seal ring scheme including a conductive second-type doped diffusion region located on the first-type substrate; and a metal conductive structure, comprising at least a metal layer and a connection conductor, wherein the connection conductor is connected to the conductive second-type doped diffusion region and to a bias provided by a first power source and to the metal layer.

Method of fabricating seal-ring structure with ESD protection

A new electrostatic discharge protection device is achieved. A p-well region is in a semiconductor substrate. An n&plus; region in the p-well region is connected to a first voltage supply. An n-well region in the p-well region is spaced from the n&plus; region such that a depletion region will extend therebetween during normal operation. A p&plus; region in the n-well region is connected to a second voltage supply of greater value than the first voltage supply during normal operation. Current is conducted through the n&plus; region to the p&plus; region during an electrostatic discharge event.

Diode for power protection

In a high voltage n-channel MOS structure, inserting p&plus; diffusion and an n-well into NMOS drain area, along with providing ESD protection by means of forming parasitic SCR, allows using signal of 5V and decreases snapback voltage below 2V.

Integrated circuit having improved ESD protection

A new method to form a LVT-SCR device in the manufacture of an integrated circuit device is achieved. The method comprises providing a SOI substrate comprising a silicon layer overlying a buried oxide layer. The silicon layer further comprises a first well of a first type and a second well of a second type. First and second doped regions of the first type are formed. The first doped region is in the first well. The second doped region is in the second well and forms an anode. Third, fourth, and fifth doped regions of the second type are formed. The third and fourth doped regions are in the first well. The fifth doped region is partly in the first well and partly in the second well. The first and third doped regions form a cathode. First and second gates are formed overlying the silicon layer. The first gate is between the third and fourth doped regions. The second gate is between the fourth and fifth doped regions. The doped regions are not separated by isolation oxide.

High voltage tolerant and low voltage triggering floating-well silicon controlled rectifier on silicon-on-insulator for input or output

A novel device structure and process are described for an SCR ESD protection device used with shallow trench isolation structures. The invention incorporates an SCR device with all SCR elements essentially contained within the sane active area without STI elements being interposed between the device anode and cathode elements. This enhances ESD performance by eliminating thermal degradation effects caused by interposing STI structures, and enhances the parasitic bipolar characteristics essential to ESD event turn on. Enabling this unique design is the use of an insulation oxide surface feature which prevents the formation of contact salicides in unwanted areas. This design is especially suited to silicon-on-insulator design, as well as conventional SCR and LVTSCR designs.

This invention provides a circuit and a method for protecting electronic circuits from electrostatic damage ESD. The invention teaches a dynamic floating silicon-controlled rectifier SCR for use as an ESD clamp. The n-well of the SCR is biased to the supply voltage Vdd under normal conditions to provide good latch-up performance. During ESD events, the n-well is floated to improve clamping performance. In addition, this invention utilizes a floating-well control circuit which provides better latch-up immunity during normal operation after the ESD event has passed.

Dynamic floating SCR (semiconductor-controlled-rectifier) ESD protection

The present invention provides a method for fabricating an ESD device. First, a substrate undergoes first implantation to form a first first-type well comprising an electrostatic discharge region. Next, second implantation is performed on the substrate and the electrostatic discharge region to form a second first-type well and an ESD device. Finally, gates, sources, and drains are formed to complete the process.

Method for fabricating an ESD device

A novel device structure and process are described for an SCR ESD protection device used with shallow trench isolation structures. The invention incorporates polysilicon gates bridging SCR diode junction elements and also bridging between SCR elements and neighboring STI structures. The presence of the strategically located polysilicon gates effectively counters the detrimental effects of non-planar STI &ldquo;pull down&rdquo; regions as well as compensating for the interaction of silicide structures and the effective junction depth of diode elements bounded by STI elements. Connecting the gates to appropriate voltage sources such as the SCR anode input voltage and the SCR cathode voltage, typically ground, reduces normal operation leakage of the ESD protection device.

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Hsinchu, Taiwan

Ta-Lee Yu