Macronix International Co., Ltd.

Ta-Hung Yang

Kuang-Chao Chen

Tuung Luoh

Chin-Ta Su

Shing-Ann Luo

Yung-Tai Hung

Ching-Yu Chang

Chin-Tsan Yeh

Sheng-Hui Hsieh

Ming-Da Cheng

Chun-Hung Lee

Chin-Cheng Yang

Ling-Wuu Yang

Chun-Yi Yang

Shih-Ping Hong

Shih-Chang Tsai

Yu-Chung Chen

Ling-Wu Yang

Chih-Ping Chen

Hsu-Sheng Yu

Chun Chiang

Chao-Lung Lo

Ming-Tsung Wu

Ming-Cheng Deng

Cheng-Yi Lin

Jen-Chuan Pan

Han-Hui Hsu

Kuo-Liang Wei

Hsin-Cheng Liu

Mao-I Ting

Chi-Min Chen

An-Chi Wei

Ling Wuu Yang

Shao-Chung Hsu

Shin-Chang Tsai

Shing-Ann Lo

Jung-Kuei Lu

De-Chuan Liu

Yih-Cheng Shih

Yukai Huang

Chun Min Cheng

Ching-Hsiung Li

Provided is a word line structure including a substrate, a stack structure, and a metal silicide structure. The stack structure is disposed on the substrate. The metal silicide structure is disposed on the stack structure. The metal silicide structure includes a first metal element, a second metal element, and a silicon element. The first metal element is different from the second metal element, and concentrations of the first metal element and the second metal element gradually decrease along a direction from a top surface of the metal silicide structure to the substrate.

Word line structure and method of manufacturing the same

A semiconductor substrate and a semiconductor device are provided in which the substrate includes a plurality of chips. Each of the chips includes at least one array region and at least one periphery region. The semiconductor substrate has a plurality of trenches disposed in the array region and/or the periphery region, wherein a ratio of the depth of the trenches to the thickness of the semiconductor substrate is between 0.001 and 0.008, and the area of all the trenches is between 5% and 90% based on the total area of the semiconductor substrate.

Semiconductor substrate and semiconductor device

An integrated circuit includes a multilayer stack, and a plurality of layered conductors extending in the multilayer stack and into a conductor layer beneath the multilayer stack. The layered conductor has a bottom conductor layer in ohmic electrical contact with the conductive layer in a substrate, an intermediate conductive liner layer over the bottom conductor layer and lining a portion of sidewall of the corresponding trench, and a top conductor layer on the top conductive liner layer.

Integrated circuit device with layered trench conductors

Measurements of line roughness are separated into groups depending upon pre-layers. Image data collected from similar pre-layer types are considered together in order to separate effects of line roughness from distortion of measurements caused by the pre-layers. The resulting line roughness measurements are used to estimate an aspect of line quality.

Measurement of line-edge-roughness and line-width-roughness on pre-layered structures

A method of forming an isolation structure, comprising: (a) providing a base having a recess; (b) forming a stop layer on the base and in the recess; (c) forming a dielectric material on the stop layer so as to allow the rest of the recess to be filled with the dielectric material; (d) removing the dielectric material over the base by performing a chemical mechanical polishing (CMP) process until a part of the stop layer is exposed so as to form a dielectric layer in the recess; and (e) removing a part of the stop layer, wherein the another part of the stop layer and the dielectric layer filled in the recess constitute the isolation structure.

Isolation structure, non-volatile memory having the same, and method of fabricating the same

An advance process control (APC) system for a plasma process machine is provided, which includes at least an optical emission spectroscopy (OES) system and an APC analysis apparatus. The OES system is used for monitoring a testing object in the plasma process machine. The APC analysis apparatus is used for analyzing the data received from the OES system.

Method of forming a deposited material by utilizing a multi-step deposition/etch/deposition (D/E/D) process

A method for manufacturing a semiconductor device is disclosed. A semiconductor substrate such as bare silicon is provided, and a dielectric layer is formed over the semiconductor substrate. An opening is provided within the dielectric layer by removing a portion of the dielectric layer. A conformal first conductive layer is formed over the dielectric layer and the opening. A conformal second conductive layer is formed over the first conductive layer. A conformal barrier layer is formed over the second conductive layer.

Semiconductor device having plural conductive layers disposed within dielectric layer

Method of depositing a silicon-containing material by utilizing a multi-step fill-in process in a deposition machine

Multivariate monitoring method for plasma process machine

An HDP-CVD process is described, including a deposition step conducted in an HDP-CVD chamber and a pre-heating step that is performed outside of the HDP-CVD chamber before the deposition step and pre-heats a wafer to a temperature higher than room temperature and required in the HDP-CVD process deposition step.

HDP-CVD process, filling-in process utilizing HDP-CVD, and HDP-CVD system

A method of fabricating metal film stacks is described that reduces or eliminates adverse effects of photolithographic misalignments. A bottom critical dimension is increased by removal of a bottom titanium nitride barrier.

Fabrication of metal film stacks having improved bottom critical dimension

A method for fabricating a patter is provided as followed. First, a material layer is provided, whereon a patterned hard mask layer is formed. A spacer is deposited on the sidewalls of the patterned hard mask layer. Then, the patterned hard mask layer is removed, and an opening is formed between the adjacent spacers. Afterwards, a portion of the material layer is removed to form a patterned material layer by using the spacer as mask.

Method for fabricating a pattern

A method for depositing a barrier layer onto a substrate is disclosed. A layer of titanium (Ti) is deposited onto the substrate using an ionized metal plasma (IMP) physical vapor deposition process. The IMP process includes: generating gaseous ions, accelerating the gaseous ions towards a titanium target, sputtering the titanium atoms from the titanium target with the gaseous ions, ionizing the titanium atoms using a plasma, and depositing the ionized titanium atoms onto the substrate to form the layer of Ti. A first layer of titanium nitride (TiN) is deposited onto the layer of Ti using a metal organic chemical vapor deposition (MOCVD) process. A second layer of TiN is deposited onto the first layer of TiN using a thermal chemical vapor deposition process. The newly completed barrier layer is annealed in the presence of nitrogen at a temperature of between about 500&#xb0; C. to about 750&#xb0; C.

Contact barrier layer deposition process

A metal pad formation method and metal pad structure using the same are provided. A wider first pad metal is formed together with a first metal. A dielectric layer is then deposited thereon. A first opening and a second opening are formed in the dielectric layer to respectively expose the first metal and the first pad metal. Then, the first opening is filled by W metal to generate a first via. Finally, a second metal and a second pad metal are formed to respectively cover the first via and the first pad metal to generate the metal pad.

Metal pad formation method and metal pad structure using the same

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Hsinchu, Taiwan

Ta-Hung Yang