Taiwan Semiconductor Manufacturing Comp. Ltd.

Ta-Ching Yu

Ru-Gun Liu

Yung-Sung Yen

Tsai-Sheng Gau

Chun-Kuang Chen

Kuei-Shun Chen

Shau-Lin Shue

Chung-Ju Lee

Chia-Tien Wu

Yung-Hsu Wu

Chih-Hao Chen

Shu-Hao Chang

Te-Chih Huang

Shih-Che Wang

Yi-Hao Chen

Chen-Yen Kao

Yuan-Fu Hsu

Chin-Hsiang Lin

Ziwei Fang

Ken-Hsien Hsieh

Chi-Cheng Hung

Wei-Liang Lin

Chen-Hau Wu

Ming-Jhih Kuo

Yu-Hsun Chen

A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.

Method of fabricating semiconductor device with reduced trench distortions

Embodiments of the present disclosure relate to methods for defect inspection. After pattern features are formed in a structure layer, a dummy filling material having dissimilar optical properties from the structure layer is filled in the pattern features. The dissimilar optical properties between materials in the pattern features and the structure layer increase contrast in images captured by an inspection tool, thus increasing the defect capture rate.

Methods of defect inspection

Various patterning methods involved with manufacturing semiconductor devices are disclosed herein. A method for fabricating a semiconductor structure (for example, interconnects) includes forming a patterned photoresist layer over a dielectric layer. An opening (hole) is formed in the patterned photoresist layer. In some embodiments, a surrounding wall of the patterned photoresist layer defines the opening, where the surrounding wall has a generally peanut-shaped cross section. The opening in the patterned photoresist layer can be used to form an opening in the dielectric layer, which can be filled with conductive material. In some embodiments, a chemical layer is formed over the patterned photoresist layer to form a pair of spaced apart holes defined by the chemical layer, and an etching process is performed on the dielectric layer using the chemical layer as an etching mask to form a pair of spaced apart holes through the dielectric layer.

Method for patterning interconnects

Directional patterning methods are disclosed herein. An exemplary method includes performing a lithography process to form a pattered hard mask layer over a wafer, wherein the patterned hard mask layer includes a hard mask feature having an associated horizontally-defined characteristic; tuning an etching process to direct etching species in a substantially horizontal direction relative to a horizontal surface of the wafer, such that the etching process horizontally removes portions of the patterned hard mask layer, thereby modifying the horizontally-defined characteristic of the hard mask feature; and forming an integrated circuit feature that corresponds with the hard mask feature having the modified horizontally-defined characteristic. Horizontally-defined characteristic can include a length, a width, a line edge roughness, a line width roughness, a line end profile, other horizontally-defined characteristics, or combinations thereof. In some implementations, the directional patterning method disclosed herein can achieve oblique interconnects and/or slot (rectangular) via interconnects.

Directional patterning methods

A method includes forming a dielectric layer over a conductive feature. A first mask having a first opening is formed over the dielectric layer. A second mask is formed over the first mask. A third mask having a second opening is formed over the second mask. A fourth mask having a third opening is formed over the third mask, a portion of the third opening overlapping with the second opening. The portion of the third opening is transferred to the second mask to form a fourth opening, a portion of the fourth opening overlapping with the first opening. The portion of the fourth opening is transferred to the dielectric layer to form a fifth opening. The fifth opening is extended into the dielectric layer to form an extended fifth opening, the extended fifth opening exposing the conductive feature. The extended fifth opening is filled with a conductive material.

Method of forming interconnect structures by self-aligned approach

A method for fabricating a semiconductor device includes forming a hard mask (HM) layer over a material layer, forming a first trench in the HM layer, which extends along a first direction. The method also includes forming a first patterned resist layer over the HM layer. The first patterned resist layer has a first opening and a second opening a second direction. The first opening overlaps with the first trench in a middle portion of the first trench and the second opening overlaps with the first trench at an end portion of the first trench. The method also includes etching the HM layer through the first patterned resist layer to form a second trench and a third trench in the HM layer and forming a first feature to fill in a section of the first trench between the second trench and the third trench.

Method of fabricating semiconductor device

Growing community of inventors

Hsinchu County, Taiwan

Ta-Ching Yu