Texas Instruments Corporation

Fujitsu Network Communications, Inc.

T-Pinn Koh

Gary Franklin Chard

Osman Koyuncu

Yilun Wang

Chung San Roger Chan

Christopher Adam Opoczynski

Adam Rappoport

Bennett Lau

Douglas Edward Wente

Mark Edward Wentroble

Maxwell G Robertson

Seuk B Kim

Steve Dondershine

Methods, apparatus, systems and articles of manufacture are disclosed to transition devices between operational modes. An example apparatus comprising: an activity detector configured to be coupled to a communication bus; a communication bus controller coupled to the activity detector; a hardware wakeup controller coupled to the activity detector; a switching circuit coupled to the hardware wakeup controller; a first oscillator coupled to the switching circuit; and a second oscillator the second oscillator coupled to the switching circuit and the hardware wakeup controller.

Methods and apparatus to transition devices between operational states

Apparatus and methods are presented for using configurable additive data scrambling or descrambling circuitry for multichannel link aggregators in which a scrambler or descrambler polynomial is specified by binary data in a programmable register, and the polynomial data is used to compute a polynomial matrix. A scrambler or descrambler pattern is computed according to the polynomial matrix, and input data is bitwise exclusive-ORed with the computed scrambler or descrambler pattern to generate scrambled or descrambled output data. The scrambling or descrambling circuitry can be reconfigured for different polynomials by reprogramming the register, with the scrambler or descrambler automatically computing an updated polynomial matrix.

Link aggregator with universal packet scrambler apparatus and method

One example includes network physical link (PHY) switch system. The system includes a multiplexer to output a first of a plurality of data streams that are input to a PHY device in response to a first state of a selection signal. The system also includes a data detector that monitors the first data stream and provides a trigger signal in response to a predetermined condition associated with the first data stream. The system further includes a switching controller that provides the selection signal, and in response to a switching command signal indicating a command to switch from the first data stream to the second data stream, monitors the data detector for the trigger signal and changes the selection signal from the first state to a second state in response to receiving the trigger signal to switch to the second data stream of the plurality of data streams.

Network physical link (PHY) switch system

An apparatus is provided. Physical medium dependent (PMD) sublayer logic is configured to communicate with a communications medium. Physical medium attachment (PMA) sublayer logic is coupled to the PMD logic. Forward error correction (FEC) sublayer logic is coupled to the PMA sublayer logic, and physical coding (PCS) sublayer logic is configured to communicate with an interface. A transmit path is coupled to the transmit data in a second clock domain to the FEC sublayer logic. A first read pointer circuit is coupled to transmit path. A write pointer circuit is coupled to the transmit path. A receive path is coupled to receive data in the second clock domain from the FEC sublayer logic. A second read pointer circuit is coupled to the receive path, where the first read pointer circuit, the second read pointer circuit, and the write pointer circuits are each configured to detect gaps between the first and second clock domains.

Physical transceiver gearbox

As part of the protocol for Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI) systems, timing circuits are used to calculate the 'round trip' latency across CPRI/OBSAI links. Traditionally, these timing circuits have been plagued with numerous problems. Here, however, a timing circuit is provided that has improved latency measurement accuracy, reduced power consumption, and a reduced likelihood of detecting a false comma. This is generally accomplished through the use of double edge latching in combination with post processing circuit and single bit transmission between low and high speed clock domains.

High resolution, low power design for CPRI/OBSAI latency measurement

As part of the protocol for Common Public Radio Interface/Open Base Station Architecture Initiative (CPRI/OBSAI) systems, multiple data rates are supported, which are each supported by one or more reference clock frequencies. Traditionally, timing circuits presently used for the physical layer (PHY) paths to determine the data rates for the serial data have been plagued with numerous problems. Here, however, a circuit that performs an automatic rate sense (ARS) of high speed serial signals in a low speed digital domain is provided, which is also relatively easy to implement and robust.

High speed digital bit stream automatic rate sense detection

A method is provided. In this method, a clock signal and an input signal are received, where the input signal is a Manchester encoded signal. A unit interval (UI) number is incremented for each UI received upon receipt of a valid UI. The UI number is compared to a plurality of threshold values after the each increment of the UI number, where each threshold value is associated with at least one of a plurality of sum values. For each threshold value, once exceeded by the UI number, its sum value is incremented for each cycle of the clock signal, and a plurality of window lengths are calculated, where each window is calculated based at least in part on at least one of the sum values at predetermined values of the UI number.

Method and apparatus for unit interval calculation

A digital circuit may have at least two asynchronous clock domains with a controller responsive to a first domain clock signal and a target responsive to a second domain clock signal. A first domain control signal pulse is generated in response to the first domain clock signal for controlling the target. Each assertion the first domain control signal pulse is detected and used to form a second domain control signal pulse synchronized to the second domain clock signal. The target is controlled using the second domain control signal pulse. If the target is a clear-on-read register, contents of the clear-on-read register are latched in a feedback register in response to the first domain control signal pulse and provided to the controller. Each bit of the clear-on-read register is reset in response to the second domain control signal pulse only if the corresponding latched content of each bit in the feedback register is a logical one.

Self-clearing asynchronous interrupt edge detect latching register

A method for decoding a Manchester-II encoded DISPLAYPORT compatible signal is provided. In this method, several counters are reset. A unit interval (UI) counter is incremented for each UI received upon receipt of a valid UI, and the value of the UI counter is compared to a plurality of threshold values after the UI counter is incremented. When the value of the UI counter exceeds each of the threshold values, for each clock cycle, a sum counter is incremented corresponding to the exceeded threshold value, and a plurality of window lengths are calculated, where each window is calculated based at least in part on the value of one of the sum counters at predetermined values of the UI counter.

Method and apparatus for unit interval calculation of displayport auxilliary channel without CDR

A system for presenting serial drive signals for effecting communication of parallel data signals includes: a controller; a serializer coupled with the controller; and a tri-state logic device coupled with the serializer. The controller provides parallel logic state signals to the serializer. The serializer treats the parallel data signals to present a serial data signal representing the parallel data signals at a first output locus, and treats the parallel logic state signals to present a serial logic state signal representing the parallel logic state signals at a second output locus. The tri-state logic device receives the serial data signal and the serial logic state signal for logical evaluation. The tri-state logic device presents the serial drive signals at a third output locus. Each respective drive signal has a respective drive state. Each respective drive state is determined by the logical evaluation.

System and method for presenting serial drive signals for effecting communication of a plurality of parallel data signals

A computer program () encoded in a computer-programmable medium, and for causing a computer to perform circuit design. The code causes the computer to perform a set of steps. The steps comprise describing a first set of circuitry and describing a second set of circuitry. The steps also comprise describing a digital signal for passing from the first set of circuitry to the second set of circuitry and detecting () transitions of the digital signal with respect to a timing constraint () of at least a portion of the second set of circuitry. Lastly, the steps comprise, responsive to detecting metastability with respect to timing of a transition of the digital signal relative to the timing constraint of at least a portion of the second set of circuitry, forcing () the digital signal to a random value and passing the random value to the second set of circuitry.

Modeling metastability in circuit design

An electronic device (). The device comprises a memory structure () comprising an integer M of word storage locations. The device further comprises a write shift register (SR) for storing a sequence of bits. The sequence in the write shift register comprises a number of bits equal to a ratio of 1/Rtimes the integer M. The device further comprises circuitry () for providing a write clock cycle to the write shift register for selected write operations with respect to any of the word storage locations. In response to each write clock cycle, received from the circuitry for providing the write clock cycle, the write shift register shifts the sequence in the write shift register. Further, one bit in the sequence in the write shift register corresponds to an indication of one of the memory word storage locations into which a word will be written. The device further comprises a read shift register (SR) for storing a sequence of bits. The sequence in the read shift register comprises a number of bits equal to a ratio of 1/Rtimes the integer M. The device further comprises circuitry () for providing a read clock cycle to the read shift register for selected read operations with respect to any of the word storage locations. In response to each read clock cycle, received from the circuitry for providing the read clock cycle, the read shift register shifts the sequence in the read shift register. Further, one bit in the sequence in the read shift register corresponds to an indication of one of the memory word storage locations from which a word will be read. Lastly, the device comprises circuitry () for evaluating selected bits in the sequence in the write register relative to selected bits in the sequence in the read register for detecting a level of data fullness in the memory structure.

First-in first-out memory system with shift register fill indication

An electronic device (). The device comprises a memory structure () structure comprising an integer M of word storage locations. The device further comprises a shift register (SR; SR) for storing a sequence of bits. The sequence in the shift register comprises a number of bits equal to a ratio of 1/Rtimes the integer M. The device further comprises circuitry () for providing a clock cycle to the shift register for selected data operations with respect to any of the word storage locations. The selected data operations are a data read or a data write. In response to each clock cycle, received from the circuitry for providing the clock cycle, the shift register shifts the sequence. Further, one bit in the sequence corresponds to an indication of one of the memory word storage locations from which a word will be read or into which a word will be written.

First-in first-out memory system with single bit collision detection

The invention includes an automated method for instantiation of a plurality of registers within an integrated circuit or integrated circuit device, including the computer-implemented steps of defining a programming language having a plurality of keywords identified with the plurality of registers, creating a control file describing the plurality of registers using the defined programming language, providing a compiling program compatible with the control file, and executing the compiling program to generate from the control file a first set of synthesizable codes containing information on traits of each of the registers. Preferably, the synthesizable codes include RTL codes. In a further embodiment, the invention includes executing the compiler program for generating an address decoder module operative n conjunction with the first set of synthesizable code through a top-level module for instantiation of the address decoder module and the plurality of registers.

Growing community of inventors

Allen, TX, United States of America

T-Pinn Koh