Cypress Semiconductor Corporation

T J Rodgers

Sam G Geha

W Alfred Graf, Iii

Shailesh Shah

Ting-Pwu Yen

Gary W Green

John Q Torode

Chris Petti

A programmable logic device includes a node and a RAM cell configured to power-up in a preferred state so as to provide a predetermined logic signal to the node upon power-up. The node may comprise an interconnection element, for example a transistor. Associated with the interconnection element may be two signal lines within the programmable logic device, for example, as part of a programmable interconnect matrix. The interconnection element and the two signal lines are associated such that when the interconnection element is in a first state the two signal lines are electrically coupled and when the interconnection element is in a second state the two signal lines are not electrically coupled. The predetermined logic signal from the RAM cell selects one of the first and second states. The RAM cell may include two PMOS transistors, each having an associated threshold voltage, wherein the threshold voltage of one of the PMOS transistors is lower than the threshold voltage of the other PMOS transistor. The RAM cell may be included in a look-up table such that the node is an output of the look-up table. Alternatively, the programmable logic device may further include a multiplexer wherein the RAM cell is coupled to the data path input of the multiplexer through the node. In other embodiments, the RAM cell may act as a select cell for the multiplexer.

Self-initializing RAM-based programmable device

A method of forming edge metal lines to interconnect features in a semiconductor device. One embodiment comprises the steps of: patterning a first insulating layer to form a first feature having a first sidewall; depositing a metal layer over the first feature; and etching the metal layer so that a first edge metal line is formed adjacent to the first sidewall. The edge metal line may be substantially anisotropically etched to form the edge metal line. The edge metal line may comprise a plurality of metal layers. The edge metal line may also interconnect features in a semiconductor device (e.g., contacts). The method may further comprise the step of forming a protective coating over a portion of the metal layer such that the etching step may form a metal interconnect line and the edge metal line from the same metal layer. The metal interconnect line may comprise a bus that may have more current carrying capacity than the edge metal line.

Edge metal for interconnect layers

A method and circuit for hiding a refresh of DRAM cells in a memory device. One embodiment of the circuit includes a selection circuit configured to select a first row of DRAM cells in the memory circuit in response to an active control signal. As a result, data may be read from or written to at least one of the DRAM cells in the first row. The selection circuit is also configured to couple a refresh address to a second row of DRAM cells in the memory circuit in response to an inactive state control signal. The second row of cells is refreshed when the selection circuit accesses the second row. For one embodiment, the DRAM cells are four transistor DRAM cells.

Dram with hidden refresh

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Woodside, CA, United States of America

T J Rodgers